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yonigo
Visitor
Visitor
10,593 Views
Registered: ‎10-14-2014

switching to Virtex-7 FPGA Gen3 Integrated Block for PCI Express

HI,

Im currently working on a project on a virtix7 vc707 device,

I must switch to a virtix7 vc709 device, and i need to recreate the pcie ip core.

My project uses a core created by '7 Series FPGAs Integrated Block for PCI Express v1.7'

and now i must switch to the new gen3 interface.

I can see that one of the differences is that once i just had a RX TX interface and now there is a requestor interface and a copmleter interface.

Is there some kind of layer i can use so that i can use my old design (RX TX) with the new core interface (completer requester)?

What whould be the easiest way to do this?

 

Thanks

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kotir
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10,570 Views
Registered: ‎02-03-2010

Hi ,

 

I believe the user application has to be modified to handle the req,cpl interfaes of Gen3 core.

There is no bridge kind of logic provided from xilinx.

 

The TX channel can be split to handle the below:

 

The Completer Completion (CC) interface is used by the user application to transmit the
completer requests.

The Requester reQuest (RQ) interface is used by the user application to generate requests
to remote PCIe® devices

 

The RX channel can be split to handle below:

 

The Completer reQuest (CQ) interface is used by the user application to deliver all received
requests from the link.

The Requester Completion (RC) interface is used by core to present the completions
received from the link in response to your requests.

 

 

Regards,

KR

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markzak
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Registered: ‎12-01-2010

I just went through the same problem myself.  I had a perfectly working PCIe Gen 2 core, and the new device only allowed the use of a gen 3 IP core.  Koti is correct, and unfortunately, there's nothing you can do about this.  You must re-write your user logic to take into account the Quad AXI-Stream interface.

The good news is that this isn't as complicated as it seems at first.  Once i finished, i realized that this separate stream interface actually made my life easer, as the completer interface (CC) no longer conflicted with my requester interface (RQ) on the transmit side.  The key is that the two separate interfaces allow concurrent completions and request.  That is, they can be put in separate modules (files), and individually modified as required.  My recommendation for you is to start with the example design for the new core, and keep editing it until you get where you need to go.
 
Good luck.

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hutchid
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Registered: ‎08-04-2010

I am currently migratin to the Gen 3 Block

 

The following gives a good summary the differences between the old and new cores.

 

http://xillybus.com/tutorials/virtex-7-pcie-gen3-1

 

I agree that the new interface makes life a bit easier for DMA

 

 

 

 

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kotir
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Registered: ‎02-03-2010

Hi,

 

Using Seperate interfaces makes channel more efficient for data transfers.

 

Actually you can refer to the PIO example design regarding the interfaces how the interfaces are handled over the user application.

 

Regards,

KR

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yonigo
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Registered: ‎10-14-2014

Thanks everyone for the help,

Im trying to start with the exampel design but i cant seem to implement it and see somthing with lspci.

If i use vivado (i prefer not to at this point) to create the example design then implement it and upload it to the fpga, i dont see anything when i use lspci. Whas i supposed to change something in the code or pin assignment?

I also tried to run the implement.sh script and upladed the routed.bit file created. still nothing on lspci.

If i try to use ise, i get this error:

ConstraintSystem:59 - costraint <NET "ext_clk.pipe_clock_i/CLK_TXOUTCLK" TNM_NET = "SYSCLK" ;> ... net not found...

What am i doing wrong? i want to see everything run on the fpga and to see it with lspci before i continue.

 

Thanks,

Yoni

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kotir
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10,315 Views
Registered: ‎02-03-2010

Hi,

 

You need to specify the location constraines as per your board.

 

It looks like this constraint does not have the entire hierarchy of your project.

Check if you can add the hierarchy from top level into the constraints and re run.

 

Regards,

KR

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