the PCIe core cannot send memory write request TLP to PC
I'm using the virtex-6 FPGA to implement a PCIe endpoint. I have a problem with sending memory write request TLP to the PC memory when developing the DMA.
I have set the bus_master_enable bit in the linux driver.
And from the view of chipscope, the trn_interface timing is fine, the buffer avalible is decreasing from 0x1e to 0, with occasionally increasing by 1, which means that the PCIe core has send several TLP out. But when it decreases to 0, the core doesn't send TLP out any more, and trn_tbuf_av is 0.
The cfg_dstatus indicates a correctalbe error all the time.
The link is in L0 state.
I want to know why the core can't send TLPs out.
I have just counted the number of TLPs that the User Application send to the PCIe core. It's 33 TLPs, and the total transmit buffer is 30. It seems that 3 TLPs has been sent out, and 30 TLPs are in the transmit buffer. But when I count the times that trn_tbuf_av increases, it's 7, which means 7 TLPs has been sent out. I don't know why it is contrary.