11-30-2014 11:08 PM
We used three KC705 evaluation platform for PCIE GEN2 X8 application at the present stage.
There are the same logic-ware in three platform. Simultaneously, we had completed DMA transmission in three platform.
In some specific test conditions, which is transmit 50Mbps and receive 240Mbps, we guarantee data is accuracy in the
DMA transmission. However, there are some bit errors in two platforms when we enhanced the test condition, which is transmit 100Mbps
and receive 400Mbps. Each error is always change from 1 to 0 at 7th bit, for example from 0x45(0100_0101) to 0x05(0000_0101).
but, another one platform is always no error.
(1) We have three KC705 evaluation platform, but we bought them at different time. First platform bought at April.2013.
the others bought at July.2014. However, the first one is always correct in our test. the others which bought later is
always exist errors in our test. Could you tell me, is there difference between two batch of KC705?
(2) Our compiler environment is ISE 14.7 and our project reference datasheet <kc705-pcie-pdf-xtp106-14.4-c.pdf>.
Is this have some effects?
(3) In KC705 Schematic <kc705_Schematic_xtp132_rev1_1.pdf>. We found Pin:MGTREFCLK1 at BANK115 is connect differential pair PCIE_CLK_Q0_P/N,
this differential pair is from PCIE card slot and frequency is 100MHz, Right?
And then, At BANK116, Pin:MGTREFCLK0 is connect differential pair SI5326_OUT_C_P/N, this differential pair is from SI5326,
and frequency is 250MHz, Right?
Could you tell me, what's difference between PCIE_CLK_Q0_P/N and SI5326_OUT_C_P/N? What's their purpose?
(4) In our .ucf file. there is :
INST "refclk_ibuf" LOC = IBUFDS_GTE2_X0Y1
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-7 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.# Please refer to the Virtex-7 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
12-01-2014 12:45 AM - edited 12-01-2014 12:50 AM
1. Are all the boards of same version (eg ver B/C/1.0 etc)? Did you run BIST test or PCIE reference design on all the three boards? Does the suspected boards work with this design?
2. It is recommended to use 14.7 reference design with 14.7
12-01-2014 05:30 AM
Are you using same PCIE slot for all boards?
If all the boards are having same version number, then reload (Reconfigure) old boards with ISE 14.7 reference designs. The ISE 14.7 reference designs for KC705 can be found in the below KC705 board link
Check the "example designs" box in the above link to view the reference designs.
Also make sure that all the switches and jumpers selections are same for all boards.
If still problem exists scope power supply rails and verify whether any noise/voltage drops in problematic boards.
12-01-2014 04:58 PM
Thanks for your reply.
1. But I don't know, where can I find board version number?
2. And I had never tried run BIST test or PCIE reference design on all the three boards.
3. All the three boards run the same bit file.
4.I think that all the reference design is almost the same.
12-01-2014 05:03 PM
Thanks for your reply.
1. I used the same PCIE slot for all the same boards.
2. The power supply is the same for all the same boards.
3. I cannot find 14.7 reference design for PCIE, I think that all reference design is almost the same for 14.x.
12-01-2014 06:09 PM
12-02-2014 03:15 AM
All the three boards have the same version number.
Now, I think that time constraint wrongs maybe lead to these errors.
But why one board is always correct.
I have no idea.