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jokul_yin
Visitor
Visitor
5,305 Views
Registered: ‎05-28-2008

too much time wasted between packets on PCIE interface

hello,

I use the Windows API functions (WRITE_REGISTER_BUFFER_ULONG,READ_REGISTER_BUFFER_ULONG) to write DMA registers of SG-DMA lists, in my windows PCIE Driver.  When I use chipscope to see the interface of PCIE, I found there is about 400ns time wasted between every posted packets from CPU to PCIE DMA registers.  And the length of packet sended from CPU, can only be 1DW. This time wasted lead a high CPU utilization and limits the bandwidth of SG-DMA. Can anyone tell me how to solve this problem? Thanks.

 

Environment:

32bit Windows XP SP2

V5 110T -1

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deepeshm
Xilinx Employee
Xilinx Employee
5,282 Views
Registered: ‎08-06-2008

The link below might be helpful to figure out what might be affecting the performance:

http://www.xilinx.com/support/documentation/white_papers/wp350.pdf

 

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vesco
Visitor
Visitor
5,008 Views
Registered: ‎08-19-2010

I would sugest that you have to set Acceptable L0 Latency to less than <64ns when you generate the core. For V5 it is set to unlimited by default. It looks like this allows the Root complex to relax the timming between write TLPs. (adds 400 ns between write (posted) packets).

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