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Adventurer
Adventurer
633 Views
Registered: ‎03-31-2014

tx_err_drop assertion in 7 series PCIe block

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Hi

 

I am using Xilinx 7 series PCIe in design.

 

PG054 says, tx_err_drop is asserted "no later than second clock cycle following axis_tlast".

 

Does it mean tx_err_drop will be asserted only after axis_tlast or it can be asserted any time the error conditions are encountered(in between a AXI stream transaction)?

 

 

Thanks

Aj.

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1 Solution

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Moderator
Moderator
788 Views
Registered: ‎02-16-2010

Re: tx_err_drop assertion in 7 series PCIe block

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Yes. Your understanding is correct. tx_err_drop will be asserted only after axis_tlast. The description of the signal behavior also gives you similar understanding.

Transmit Error Drop: Indicates that the core discarded a packet
because of a length violation or, when streaming, data was not
presented on consecutive clock cycles.
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1 Reply
Moderator
Moderator
789 Views
Registered: ‎02-16-2010

Re: tx_err_drop assertion in 7 series PCIe block

Jump to solution
Yes. Your understanding is correct. tx_err_drop will be asserted only after axis_tlast. The description of the signal behavior also gives you similar understanding.

Transmit Error Drop: Indicates that the core discarded a packet
because of a length violation or, when streaming, data was not
presented on consecutive clock cycles.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post