tx_err_drop assertion in 7 series PCIe block

[ajasan]

Hi

I am using Xilinx 7 series PCIe in design.

PG054 says, tx_err_drop is asserted "no later than second clock cycle following axis_tlast".

Does it mean tx_err_drop will be asserted only after axis_tlast or it can be asserted any time the error conditions are encountered(in between a AXI stream transaction)?

Thanks

Aj.

[venkata · Accepted solution]

Yes. Your understanding is correct. tx_err_drop will be asserted only after axis_tlast. The description of the signal behavior also gives you similar understanding.

Transmit Error Drop: Indicates that the core discarded a packet
because of a length violation or, when streaming, data was not
presented on consecutive clock cycles.