04-03-2018 06:24 AM
Hi
I am using Xilinx 7 series PCIe in design.
PG054 says, tx_err_drop is asserted "no later than second clock cycle following axis_tlast".
Does it mean tx_err_drop will be asserted only after axis_tlast or it can be asserted any time the error conditions are encountered(in between a AXI stream transaction)?
Thanks
Aj.
04-05-2018 08:56 AM
04-05-2018 08:56 AM