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Observer babu_image@
Observer
1,206 Views
Registered: ‎10-25-2017

unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

Hi guys,

Currently I am using this UltraScale Devices Gen3 Integrated Block for PCI Express v4.4 LogiCORE IP  from vivado tool . Instead of Xilinx design ,I used my design and I am able to do single write and single read. but I am unable to  do multiple writes and multiple reads. I m not understanding where I need to change the code for multiple writes and multiple reads. can you guys please help me out.

https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf

the above link tells about what I am using.

Thanks in advance !!!!!!

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6 Replies
Xilinx Employee
Xilinx Employee
1,166 Views
Registered: ‎07-26-2012

Re: unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

Which transaction does not work well in PG156. Can you let me know the figure number or page?

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Observer babu_image@
Observer
1,159 Views
Registered: ‎10-25-2017

Re: unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

thanks Kurihara for your reply.  I don't much more about the waves and I will explain the things, .using this vivado IP example design ,inbuilt pio_writereadback_test0  test case is there. using this test case I am able to run the single read and write transaction, but I am unable to do multiple write and read transactions using this example.

page no:261 ----test case(pio_writereadback_test0) is there.

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Xilinx Employee
Xilinx Employee
1,138 Views
Registered: ‎07-26-2012

Re: unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

If you use MEM 32 space for BAR, as an easy way to see multiple Write & Read, please change the following tasks in sample_test.vh:

 

board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.RP.tx_usrapp.DEFAULT_TAG,
board.RP.tx_usrapp.DEFAULT_TC, 11'd4,  // changed from 1 to 4
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10,
4'hF, 4'hF, 1'b0);                                    // changed from 4'h0 to 4'hF

 

board.RP.tx_usrapp.TSK_TX_MEMORY_READ_32(board.RP.tx_usrapp.DEFAULT_TAG,
board.RP.tx_usrapp.DEFAULT_TC, 11'd4,     // changed from 1 to 4
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10,
4'hf, 4'hF);                                               // changed from 4'h0 to 4'hF

If you need more than 4 DW length, the tasks has to be modified.

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Observer babu_image@
Observer
1,124 Views
Registered: ‎10-25-2017

Re: unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

Hi Kurihara,

    Thanks for you. actually i need to write the data to particular register addresses(8'h10 is default address instead of that i am using 32'h0008000 according to my design) ,so each and every time i need to write the data into different addresses ,like that i need the things want from you.

 

 

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Observer babu_image@
Observer
1,123 Views
Registered: ‎10-25-2017

Re: unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

Hi Kurihara,

 

    need to compare the write and read data whether it is matching or not. by default(xilinx gave ) for 1 write and 1 read it is working fine. how can we compare multiple writes and reads.

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Xilinx Employee
Xilinx Employee
1,083 Views
Registered: ‎07-26-2012

Re: unable to do multiple reads using this PCI Express v4.4 LogiCORE IP

The target address can be changed in the task. If it's fixed one, it should be replaced with the current argument.

 

But I think the example test bench does not have prepared a task to compare between multiple data of WRITE and READ. 

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