Does virtex-5/6 support concurrent bi-directional bus-master DMA?
Page 8 of XAPP1052, under the section of Initiator Logic, says that this reference design supports one type of data flow at a single time, either upstream or downstream. Jungo's Windriver sample codes (bmd_degisn) also supports only one direction of data buffering at a time, either read or write.
I'm just wondering if virtex-5/6 PCIe Core supports bi-directional bus-master DMA, i.e., concurrent data buffering from FPGA to PC and from PC to FPGA. Thank you.