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jmonteiro-dme
Explorer
Explorer
8,865 Views
Registered: ‎05-15-2009

virtex 6 only supports x1 lane?!

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Hello,

 

While generating a XPS project with the PCIe bridge core i got this error:

 

ERROR:EDK:3193 - issued from TCL procedure "check_family_parameter_settings" line 25
 PCIe_Bridge (plbv46_pcie) -
 virtex6 only supports x1 lane configuration

 

How can this be? My ML605 has a 8 lane (x8) PCI header. What am i missing?

 

 

Best,

JM

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tushar_dongre
Xilinx Employee
Xilinx Employee
10,675 Views
Registered: ‎02-25-2009

Probably this is because of the fact that plbv46_pcie has been developed and tested only for x1 lane, as is mentioned in following doc:

 

http://www.xilinx.com/support/documentation/ip_documentation/plbv46_pcie.pdf

 

However, you will see the improvement in future releases.

 

Thanks,

 

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tushar_dongre
Xilinx Employee
Xilinx Employee
10,676 Views
Registered: ‎02-25-2009

Probably this is because of the fact that plbv46_pcie has been developed and tested only for x1 lane, as is mentioned in following doc:

 

http://www.xilinx.com/support/documentation/ip_documentation/plbv46_pcie.pdf

 

However, you will see the improvement in future releases.

 

Thanks,

 

View solution in original post

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jmonteiro-dme
Explorer
Explorer
8,802 Views
Registered: ‎05-15-2009

Thanks, however the PCIe x1 bridge design is not working (the ML605 is not detected by windows when inserted in the x8 PCI slot). I tried to change J42 from x8 to x1 but it is still not detected.If i use a x8 reference design the board is detected.

 

What am i missing?

 

 

Best,

JM

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jmonteiro-dme
Explorer
Explorer
8,752 Views
Registered: ‎05-15-2009

Taping the unused lanes from pins B19 and A19 inclusive to B49 and A49 did the trick.

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namdeguerre
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Registered: ‎08-30-2010

Hello, When is it expected to have the PLB wrapper support x4/x8 gen2 configuration? 

 

Also, to confirm, currently, if we want to use the ML605 at x4 Gen2 speed, EDK (XPS) cannot be used, right? The PCIe core has to be generated in coregen and use in ISE tools only, right?

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jmonteiro-dme
Explorer
Explorer
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Registered: ‎05-15-2009

Hi,

 

It depends on what you want to do. You can use x4 or x8 Gen2 designs if you want to implement a memory controller. Check the reference designs at http://www.xilinx.com/products/boards/ml605/reference_designs.htm . For this you can use coregen, no need for ISE.

 

If you want to use the PCIe bridge then at the time being only the x1 design is available, hence only one lane can be used. This is done in XPS.

 

 

Best,

JM

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jennychang2011
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Registered: ‎03-08-2011

Hello,

 

I'm searching through the discussion about pcie test. 

I got a new ML605 board (Virtex6) and tried to run the PIO reference design on it.   the board inserted in the PC PCI slot but the board canot be detected-based on reading of PCITREE on windows XP.

 

you said you could detect the board if you ran x8 reference design? 

so my quesiton is:  1) what is the setting on the S2 setting?  did you set to 011001?  or kept the defualt setting?

2) when you insert the board into the pci slot, did you set anything on the motherboard to make sure the lane is x8? 

 

I don't know what went wrong here.  could you help?

 

thanks,

Jenny

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jmonteiro-dme
Explorer
Explorer
7,739 Views
Registered: ‎05-15-2009

Hi,

 

1) My S2 settings are 100110 (from dip 1 to 6)

 

2) No, the lane negotiation is automatically done in boot cycles. Actually i use the PCIe bridge (x1) in a x8 slot but for the board to be detected by the OS i had to tape out the unused lanes. The x8 reference design directly worked in a x8 slot.

 

Make sure your have the bitstream stored in the xcf128x flash since it has a dedicated oscillator to speed up the configuration (at boot) in order to fulfill the PCIe requirements (see page 20 of the ML605 HW user guide).

 

 

Best,

JM

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