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Newbie
Newbie
427 Views
Registered: ‎11-26-2020

vivado 2020.1 vs 2020.2

Dear,

I am using vivado 2020.1 with the pcie patch https://www.xilinx.com/support/answers/75334.html

Someone knows if the bug posted below is fixed in 2020.2?

  • Bug Fix: Fixed the intermittent config read hang in Bridge Mode Root Port config

Best,

Alen.

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3 Replies
Explorer
Explorer
422 Views
Registered: ‎07-20-2018

Hi @alen_89 ,

here is the changelog for pcie4c_uscale_plus_v1_0 in Vivado 2020.2:

2020.2:
* Version 1.0 (Rev. 10)
* Bug Fix: Fixed the intermittent config read hang in Bridge Mode Root Port config
* Bug Fix: Fixed VU19P device support issue
* Bug Fix: Fixed TXOUTCLK constraining issue, which exists in the last release.
* Other: Added XCZU43DR and XCVU57P device support.
* Other: Updated IBUFDS_GTE4 parameters for 250 MHz reference clock designs
* Other: Fixed few IP related warnings, which do not alter IP functionality.
* Revision change in one or more subcores

You can find it in:

Vivado/2020.2/data/ip/xilinx/pcie4c_uscale_plus_v1_0/doc/pcie4c_uscale_plus_v1_0_changelog.txt

I think the answer is yes.

Cheers.

Newbie
Newbie
411 Views
Registered: ‎11-26-2020

Thank you very much @dsakjl
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Explorer
Explorer
402 Views
Registered: ‎07-20-2018

Hi @alen_89 ,

you're welcome!

Please, accept my first reply as solution to mark this post as solved.

Cheers.

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