11-26-2020 01:29 AM
I am using vivado 2020.1 with the pcie patch https://www.xilinx.com/support/answers/75334.html
Someone knows if the bug posted below is fixed in 2020.2?
11-26-2020 01:44 AM
Hi @alen_89 ,
here is the changelog for pcie4c_uscale_plus_v1_0 in Vivado 2020.2:
* Version 1.0 (Rev. 10)
* Bug Fix: Fixed the intermittent config read hang in Bridge Mode Root Port config
* Bug Fix: Fixed VU19P device support issue
* Bug Fix: Fixed TXOUTCLK constraining issue, which exists in the last release.
* Other: Added XCZU43DR and XCVU57P device support.
* Other: Updated IBUFDS_GTE4 parameters for 250 MHz reference clock designs
* Other: Fixed few IP related warnings, which do not alter IP functionality.
* Revision change in one or more subcores
You can find it in:
I think the answer is yes.