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Observer
Observer
13,176 Views
Registered: ‎09-01-2014

write_bitstream error for Tandem_PROM

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INFO: [Designutils 12-2358] Enabled Tandem boot bitstream.
ERROR: [Designutils 20-1854] The CONFIG_MODE constraint must be set for the Tandem PROM flow.

 

 

This is with Vivado 2015.4.1 and for xcku060-ffva1156-2-i target.

PCIE_3_1_X0Y0 in x4 mode with Quad224

 

HELP!

 

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Scholar
Scholar
25,335 Views
Registered: ‎06-05-2013

@chili.chips Please add constrain in your xdc. I belive you are using bpi x16 so these constrains can be copied as it is in your xdc and then re-run

 

set_property CONFIG_MODE BPI16 [current_design]

-Pratham

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Scholar
Scholar
25,336 Views
Registered: ‎06-05-2013

@chili.chips Please add constrain in your xdc. I belive you are using bpi x16 so these constrains can be copied as it is in your xdc and then re-run

 

set_property CONFIG_MODE BPI16 [current_design]

-Pratham

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View solution in original post

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Scholar
Scholar
13,160 Views
Registered: ‎06-05-2013

@chili.chips Please check these links which would be helpful

 

From page no 84 of the UG

http://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_1/pg156-ultrascale-pcie-gen3.pdf 

Video

https://www.youtube.com/watch?v=XVDwEfzrntA

 

-Pratham

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Observer
Observer
13,154 Views
Registered: ‎09-01-2014

Thanks!

Are there CONFIG_MODE(s) that cannot work in Tandem-PROM mode?

BTW, I was selecting CONFIG_MODE via Bitstream Settings GUI, but that didn't seem to have an effect. Why???

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Scholar
Scholar
13,143 Views
Registered: ‎06-05-2013

@chili.chips Yes there are.

 

Selecting via GUI should also work (This adds the same tcl command in your xdc). Did you save design/constrain file?

-Pratham

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Observer
Observer
13,043 Views
Registered: ‎09-01-2014

Could you please enumerate all CONFIG_MODEs that are:

   1) interoperable with Tandem-PROM

   2) and NOT

 

When changing constraints through the GUI (and also TCL console), I did not save them, but just initiated bitstream generation after constraint change.

 

I thought that, with Implemented Design opened / loaded in memory, the typed-in constraints would apply directly to it and remain effective for the next flow step (write_bitstream) in that session. In other words, saving constraint would be needed only if I wanted to preserve typed-in changes for the next run/session from the scratch.

 

How are we supposed to go about interactive experimenting/exploration of constraints (trial-and-error) without ruining our main/reference constraints files?

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