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Visitor yuripoddobny
Visitor
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Registered: ‎08-28-2019

xDMA addressing spaces

In our system we use DMA over AXI4-Stream user interface (C2H and H2C channels with buffer descriptors) and we shall access internal xDMA registers for its configuration and control. I am unclear how to properly define access to xDMA internal registers. In the documentation pg195 it is written that it is possible over BAR0 (enabling AXI-Lite Master and connecting it to AXI-lite Slave) and somehow over BAR1.  

Also I am unclear if we shall explicitely define over BARs DMA addressing space for AXI4-Stream user interface. 

Appreciate your help,

Yuri

 

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