03-01-2021 03:52 PM
I'm having issues generating xdma interrupts ported on a Kintex 7 325 using a Questa Sim-64 2020.3 simulation. I've configured the Ultrascale Root Port and the Kintex 7 Endpoint per AR's 58495 and 72702. I've debugged the simulation down to the xdma_v4_1_6_udma_wrapper, which is locked. Signals go in and nothing comes out. I've tried Legacy, MSI, and MSI-X. I don't see any cfg_msg_* message traffic and the 'cfg_interrupt_sent' signal(which comes out of the udma_wrapper) is 'x'. The XDMA configuration is very simple, so I'm at a loss as to why the simulation is not working. Thanks, in advance, for any assistance.
03-04-2021 09:33 AM
Can you explain the steps you implemented based on AR#72702 with XDMA IP?
03-05-2021 03:52 PM
Sorry for the delay, but I wanted to double check everything before responding. I followed the steps in the MSI-X Interrupts section on page 9 of the AR#72702. I've attached my simulation log. In it you'll find every access made during the simulation. There is a section where I dump the Root Port PCIe Configuration Space, and the Endpoint Configuration Space. Also, the log file shows accesses to setup interrupts within the XDMA IP. I've also attached a simulation capture showing MSI-X interrupt signals. When interrupt_requests go active, the cfg_interrupt_msix_int line stays inactive, and the cfg_interrupt_sent signal is 'X'. The screenshot also shows the Endpoint Message Interface h'z. I've also attached the transmission_core_dma_controller_0_core_top.sv file. The parameter configurations might give you some insight.
Finally, my first thought was that this maybe a simulation issue, but running the device on the platform reveals the same thing. Interrupts don't work. When we run the polling test, things work great.
03-10-2021 05:17 PM
Hi @kas ,
I referred to the log. I could not verify step #2 - The Function Mask in MSI-X Control register must be unset. Can you confirm?
One more thing, whether usr_irq_req input is asserted in synchronous to axi_aclk output from the IP?
03-11-2021 07:00 AM
Line 829 of the Log File displays the value of the MSI-X Control Register. Also, the entire system is running off the axi_clk from the XDMA, so yes to usr_irq_req input.
03-18-2021 07:40 PM
Can you share the IP .xci file? I would like to check the issue using IP example design.
03-31-2021 04:29 PM
I ran simulation of MSI-X interrupts using IP example design generated with your .xci file. I could do the required settings and trigger one interrupt successfully. There are no additional steps other than those mentioned in AR#72702. The snapshot below shows my result.
I have attached the test bench update I did for this test. Refer to the attachment from line 348. Can you compare the steps in my test bench and yours?