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pangwenbin
Observer
Observer
1,299 Views
Registered: ‎07-10-2018

xdma tandem- help me

I am trying use xdma which is selected with tandem.

i have selected a device kcu1500, the xdma which selected the Advanced configuration Mode option, and selected Tandem for the Tandem Configuration or Partial Reconfiguration option.

Then i got a example design .I try to synthesize and implement and  generate bit and then prom files ,it looks very well.

But i add a vio and mark_debug into the design ,these is a error dure implement.The error means CONFIG cells is not marked to stage 1.So i add the fellow constraint into xdc file.

set_property HD.TANDEM 1 [get_cells dbg_hub]
set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub]
 Then that error looks be solved.But a ner error occur:

[DRC HDTC-4] Stage one Pblock logic must be contained: Stage one Pblock 'xdma_0_i_inst_pcie3_ip_i_inst_xdma_0_pcie3_ip_Stage1_main' has cell 'dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck' placed at site BUFGCE_X2Y32 which is not within the allowed range for this Pblock.

Now it has took me someday,anyone give me some help?

 

 

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2 Replies
deepeshm
Xilinx Employee
Xilinx Employee
1,230 Views
Registered: ‎08-06-2008

Can you please check if this helps?
https://www.xilinx.com/support/answers/62192.html
davidd
Xilinx Employee
Xilinx Employee
1,222 Views
Registered: ‎11-17-2008

@pangwenbin,

 

By assigning the dbg_hub module to stage 1 via the properties you note, you expect all of that logic to be available with the base PCIe IP when stage 1 programming completes.  All stage 1 logic must be assigned to a stage 1 pblock.  There are two to pick from, so the specific resources must be available within the target region.  Stage1_Main contains the PCIe block, fabric logic (BRAM, CLBs), transceivers, and the CONFIG_SITE, which is where the BSCAN is located.  But this clock buffer is looking for a BUFGCE resources, which can be found in the Stage1_Config_IO pblock.  Try the following:

 

set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck]

 

Note that some debug logic is inserted during opt_design, so simply adding this to a general implementation XDC will not work, as unmatched instances will be thrown out.  As @deepeshm notes in his link to the AR, these constraints must be added prior to place_design for them to be attached to the updated design that includes debug logic.  Another example of this is the assignment of the BSCAN instance to stage 1, like so:

 

set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]

 

thanks,

david.