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Voyager
Voyager
227 Views
Registered: ‎05-30-2017

zcu106 vcu trd 2019.1 PCIe trancode pcie_reg_space address question

Hello,

I'm working with vivado 2019.1 and zcu106. I'm making some test with vcu PCIe transcode example design. I did some transcoding and it works. Looking at the vivado project of the design I observed that BAR0 is 32 MByte but pcie_reg_space IP mapped on BAR0 have an address offset of 0x44A0_0000 byte so it is out of addresable BAR0 space. Is this a mistake? Why the design works however?

Thanks.

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Voyager
Voyager
165 Views
Registered: ‎05-30-2017

Re: zcu106 vcu trd 2019.1 PCIe trancode pcie_reg_space address question

Could anyone exaplain me how pcie_reg_space peripheal could be addressable also if it has this great offset. Ther is something that I didn't understand. Thank you very much.

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