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Registered: ‎05-07-2017

zynqMP soc PS PCIe serder clock can not lock, reg:0xfd4023e4 returns 0x01 always.

We have a custom board with a programmable clock source generating 4 clocks ( all set to 100MHz for debug purpose. Those 4 clocks are connected to PS-GTR reference clock pins.

 

When we assign refclk2 to PCIe (takes 1 lane, lane0), on boot, we always get PLL lock status register read 0x01,( register 0xFD4034E4). As a result, we can not debug program with JTAG, since the mask poll of the register will pop  a timeout error message.

 

To check whether refclk2 is ok or not, we add one more device, a USB 3.0 device, uses GT lane1, and assign refclk2 as its reference clock. To compare, we assign refclk0 to PCIe device. Boot the board, and check clock PLL status, the result is, lan0 PLL status still return 0x01 (0xfd4023e4) , lane1 for USB device, its reference clock refclk2 get locked, status register 0xfd4063e4 return 0x38.

 

We don't know why the same clock returns different status when assigned to a different device (here, PCIe and USB). Do the clock lock conditions different for different device??

 

What does lock status value 0x01 (pll_coarse_code_msb_status_read) mean?

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

 

What's the required LVDS voltage for the clock, the following image is taken at the clock source (single-end), does it fulfill the requirements?

clk_20190925213829.jpg

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