One of the most mysterious elements of the data sheets is the relationship between the numbers in the data sheet and the speeds files which describe the timings which are built into the software. Here is a news flash: “Problem Solved.”
If we look ahead to page 13 for “Switching Characteristics:”
We first see the various grades of performance (speeds grades) available for the Virtex-7 family. -1L is the slowest, and -3 is the fastest device. The -1L is specified to operate at 0.90V for the core (Vccint), and has lower power with a guaranteed level of performance. The 1 is the slowest speed grade for 1.0V operation. -3 is the fastest speed grade that operates from a 1.0V core supply.
All of the performance numbers are worst case, with the voltage supplies inside their recommended operating range.
The devices are tested such that they will meet the specified numbers.
When devices are released to production, you should check to make sure your software release is using the production qualified speeds file database, as indicated in Table 23. Prior to production release, while devices are in the engineering sampling phase, timing has not been finalized and test programs are still being optimized. The speeds files in the early software releases are intended to be more pessimistic that they may be otherwise, but not all paths are fully characterized and verified.
The next section is on I/O speeds and delays. Read the measurement methodologies in tables 27 and 28, as they define the conditions under which the numbers apply.
The following pages contain the ILOGIC, OLOGIC and other specialized I/O function timings.
Then, at Table 34 the CLB internal timing numbers begin.
At Table 37, the block RAM (BRAM) and BRAM FIFO numbers are presented.
Then, at Table 38 the DSP48 performance is detailed.
Following that are the configuration block timing numbers, the clocking resource performance numbers, and finally, the multi-mode clock manager (MMCM) performance numbers.
That’s a Lot of Numbers!
Yes, there are a lot of numbers in the data sheet, but they are all part of a larger set of numbers which we call the speeds files. The speeds files are built into the ISE tools so that the tools can govern the place and route and the resulting design can meet its timing constraints. For details on the timing, one can interrogate any net or resource using FPGA_Editor, and there are ‘verbose’ report modes for the tools to report more information on the nets in your design.
It is often the best practice to try to synthesize, constrain, and place and route a small design to get an idea of its performance. To perform the task by hand using the data sheet numbers would be far too difficult, and you would be unable to choose something as a route delay (as routes get placed where they meet timing).
One may compare numbers from similar tables for previous technology devices, but actual performance depends on more than just the numbers in the speeds files. Routing resources, improvements in the synthesis tools, or improvements in the architecture are not represented in a few numbers.
In the next part, we will examine the other modules of the data sheet.