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Package Generated Alpha Particles: They are a Problem and Here is the Information

by Xilinx Employee on ‎11-12-2009 02:47 PM (5,737 Views)

Package Generated Alpha Particles:  They are a Problem and Here is the Information

 

There are two sources of alpha particles and both cause upsets:


1) Atmospheric neutrons that slam into the silicon result in alpha particles.  In this blog, we will refer to these as atmospheric upsets which result in soft errors.
2) Alpha particles generated by device package materials.  We will refer to these as package alphas which also contribute to the soft errors.

As an industry first, Xilinx has summarized both sources for its Single Event Upset (SEU) soft error rates in its latest quarterly reliability report:

http://www.xilinx.com/support/documentation/user_guides/ug116.pdf

Package Generated Alpha Particles

For the first time, Xilinx has reported the package alpha particle contribution to the overall soft error rate.  Note that Xilinx continues to lead in being completely open and honest about upset rates.  No other manufacturer publicly releases this information (what are they hiding?  A lot!).

Why Does Xilinx Not Show Previous Families Having Package Alpha Upset Rates?


Prior to the latest technology node at 45/40 nm, package alpha particle upset rates were determined to be less than one quarter (<25%) of the New York City (sea level) atmospheric upset rate.  The testing is detailed in the underground (~1,650 feet below ground) test reports, from Rustrel found at:

 

http://www.xilinx.com/support/documentation/white_papers/wp286.pdf: http://www.xilinx.com/support/documentation/white_papers/wp286.pdf

 

As some of you may know, Xilinx experienced a package alpha contamination issue awhile back:

http://www.xilinx.com/support/documentation/white_papers/wp286.pdf

We not only publicly acknowledged the problem, we issued a recall.  This was an expensive lesson to learn, and it resulted in many positive changes.

What is Different Now?

We continue to evaluate the package alpha sensitivity of our products, and we have progressed from low alpha materials to ultra-low alpha materials for assembly.  The best materials available today are being used, and, unfortunately, they are not quite good enough for us to continue ignoring the package alpha contribution to the atmospheric alpha upset rate.

Package alpha emission varies from lot to lot, batch to batch, and is often as much as 10:1.  All lots must have “certificates of compliance” on record for their use, but the equipment used to test these batches is not sensitive enough to measure the quality of every batch.  Thus, in the past we have seen package alpha upset rates as low as 8 to 20 FIT/Mb (basically, in the noise), and we have seen some that are at 25% of atmospheric upset level.

At 40 and 45 nm (Virtex®-6 and Spartan®-6 FPGA), the packaging materials, even with the best the industry can offer, are now at the point where the package alpha upset rate is predicted to be more than 25% of the atmospheric upset rate at sea level.  It will often be less, but we cannot guarantee that.

Although we haven’t measured any of the latest devices underground yet, we have performed the same tests that we performed on all new technologies, and the predicted package alpha upset rates are ~50% of the atmospheric upset rate at sea level for Virtex-6 FPGA, and ~100% of the atmospheric upset rate at sea level (equal) for Spartan-6 FPGA.

ASIC and ASSP vs Xilinx FPGAs


We have previously shown selected customers that in ASIC and ASSP products soft error upsets in memory were surpassed by their soft error upsets in logic at the 45 nm node.

http://www.public.asu.edu/~ashriva6/teaching/CES/CES_Spring_2008/SoftErrorsInAdvancedComputerSystems.pdf

(Figure 5)

What does this logic upset rate mean for customers of ASSP and ASIC products?  It means that transient upsets due to atmospheric and package alphas now dominate the upset rate at these advanced technology nodes.  The combination of the small size of the logic structures and the gigahertz clock rates means that a 100 ps transient upset will be “caught” by the next latch of a flip-flop and become a functional fault, or failure.

Thanks to more robust logic structures, Xilinx FPGA devices continue to have negligible non-configuration bit related upset rates (measured at less than 1.5 FIT per million DFF in Virtex-5 FPGA).  A design in an ASSP or ASIC will be more sensitive to upsets than the same design in a Virtex-6 or Spartan-6 FPGA!  Using the mitigation methods we suggest, the design in the Xilinx FPGA can be made an order of magnitude more reliable (less likely to fail due to a soft error).

Calculating SEU Error Rates


To determine your design’s susceptibility to SEU, first find the upset rate for your location:

http://www.seutest.com/cgi-bin/FluxCalculator.cgi

The upset rate for New York City is 12.9 neutrons per cm2 per hour.  Your location will be different.  You may scale the reliability report FIT/Mb for your location from the value at New York City.  For example, Albuquerque, New Mexico, has roughly four times the flux of atmospheric neutrons of New York City (upsets will happen four times more often).

Multiply this resulting location’s FIT/Mb by any building attenuation factor:  each six inch thick floor of a typical steel reinforced concrete building attenuates by about 0.88.  Add to this location specific and scaled FIT/Mb number for atmospheric neutrons the predicted package alpha upset rate.  Then, multiply the sum of the atmospheric alpha and the package alpha FIT/Mb by the configuration Mb in the part chosen.  When this is done, divide the result by 10 to account for critical bit usage (not every bit is critical).  This result is the FIT/device for the configuration memory.

In a similar fashion, for the Block RAM take the location adjusted FIT/Mb, adjust for building attenuation, and add the package alpha contribution.  Then, multiply by the Mb of Block RAM used.  There is no additional adjustment for Block RAM.  If the Block RAM FIT per device is too high, use Block RAM ECC which will result in 0 FIT/Mb (that is, you may safely ignore the soft failure rate of Block RAM).

Adding the configuration FIT/device to any remaining Block RAM FIT/device yields the total FIT/device for your design.

If you have any difficulty with this process, consult your FAE for assistance.

Good News

The good news is that although we must now include package alpha upset rates in reliability calculations, the intrinsic failure rates are still very low.  If the resulting failure rate is still too high for your application, Xilinx provides additional tools to help mitigate errors.  Xilinx FPGAs have FRAME_ECC to enable finding and fixing configuration bit errors, as well as other tools and IP to help you achieve any desired overall system failure rate.  In fact, Xilinx has solutions that enable its products to be used in the radiation intense environment of space.

And remember, ASIC or ASSP soft failure rates are now much worse at 45 nm, and the package alpha problem with ASIC and ASSP are now leading to quiet recalls (no public acknowledgement of a problem).  Some ASIC vendors are reporting ten times as many upsets due to package alphas than as atmospheric alphas at sea level (if they report at all).

Austin Lesea