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Timing Constraints: Part 1 (of 5)

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Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users.  In order to help those who have never had to constrain their timing, I offer the following part one, of five parts, on timing constraints.

Some Basics

Timing constraints apply to nets or networks, the path or paths taken from one element to all of the inputs of subsequent elements.  One can also call out a specific path that is part of a net or network.

Every design should have at least one period constraint that specifies the clock and the duty cycle of the clock.  A clock is always required for synchronous design, and so the period constraint is the most basic and is always a required constraint for any design.  If there is more than one clock, each requires its own period constraint.

The period constraint will define how all nets must be routed in order to meet the timing requirements for proper operation.

A group may be defined to generically refer to many nets or paths of a selected set, such as a bus or control group.


When it comes to having many constraints for a design the following applies:   the more general the constraint, the lower its priority, and, conversely, the more specific a constraint, the higher the priority.  For example, a period constraint on a clock net or network is very general and will be over-ruled by a from:to constraint on a specific net or network.

The specific constraint for the from:to  (or from:thru:to) is deemed more important than the more general constraint for any net  within a clock domain.

There is a timing specification interaction report (the .tsi report) that details how the constraints interact.  Select this option in the timing analyzer for reporting if you have a set of constraints, and you need to know how they are interacting and which priorities have been set.

One can override the assumed priorities and manually set the priority of any timing constraint.  The use of the priority command allows setting a very low priority, such as 0, or even a negative priority, such as -10, which will be evaluated with an even higher priority than 0.

Example 1

The PERIOD constraint only covers nets from Synchronous Elements to Synchronous Elements, such as FFS to FFS, as shown in blue below:

NET "clk20" TNM_NET = “tnm_clk20";
TIMESPEC "TS_clk20" = PERIOD “tnm_clk20" 20 ns HIGH 50 %;

A TIMEGRP (timing group) is created called tnm_clk20 which contains all of the downstream synchronous components that net clk20 drives.  All of the paths between these synchronous elements are then constrained with the timing specification TS_clk20, which specifies a 20 ns requirement from synchronous element to synchronous element and a HIGH 50% (clk20 has a 50/50 duty cycle).

Example 2

FROM:TO constraints are used to define a requirement for paths that go between two groups.

TIMESPEC TS_my_fromto = FROM my_from_grp TO my_to_grp 40 ns;

tells the tools that you need to ensure that data makes it from the components in the timing group ‘my_from_grp’ to ‘my_to_grp’ in 40 ns.  Timing Analyzer will still calculate the clock skew from source group to destination group, but at a lower priority  (if the clocks are related).  Predefined groups can be used, for example:


If we need leave out the time unit (ns, ps, etc…), then the tools presume ns:


You can leave FROM or TO off of the constraint and make it more generic:


All of the FROM:TO constraints in the examples above would be of higher priority than the PERIOD constraint.

TSI Report

The TSI report is generated with the ‘-tsi design.tsi’ switch in the TRCE command line, or by specifying the option in the timing analyzer.  If a user does not see a path under the correct constraint, this is the best place to start.  This report will also make suggestions on ways to improve constraints in the universal constraints file (UCF).  This report will also notify the user of any paths that are constrained by multiple clock domains:

Example 3

Constraint Interaction Report

Constraint interactions for TS_clk0_1 = PERIOD TIMEGRP "clk0_1" TS_clk HIGH 50%;
          1 paths removed by TS_my_fromto = MAXDELAY FROM TIMEGRP "my_to_grp" TO TIMEGRP "FFS" 40 ns;

Analysis of Example 3

In other words, the FROM:TO constraint (just one) was applied ahead (higher priority) of the PERIOD constraint.

Next time we will discuss setup and hold.

Austin Lesea


Constraints Guide:  Constraint Syntax for UCF, PCF,  and HDL:

Timing Constraints User Guide:  Conceptual information on how to constrain a design:

Timing Analyzer Help:  General information on how to use timing analyzer:
Message Edited by austin.lesea on 12-22-2009 09:48 AM


Thank you for your great and useful information on Timing Constraints.

I looked every where in the timing analyzer - ISE10.1 - but I couldn't find somewhere to set TSI report.

I also tried typing it in the command console "-tsi main_prj.tsi" but I only receive below warning message:


"Command "-tsi" not understood "


would you please declare where it can be set.




1. In Project Navigator select File > Open > Reports and select a *.tsi file. This will open the report in the ISE Text Editor 2. Select Open. The Open dialog appears. 3. Select the category Reports and select the TSI report you want to open. 4. Select Open. The Constraints Interaction report you selected opens in the Workspace window. (from the software manuals...)

Hi Austin,


Thank you for your answer, it worked.




We need to enable "Generate Constraints Interaction Report" option from process properties of "Implement Design".


Hi Austin, I, a newbie in using xilinx tools. I just happen to read your informative blog on using timing constraints in xilinx. I have read the ug612.pdf on using timing constraints and "constaints guide" by xilinx. I have a problem to start with using PERIOD constraint in my design:- You mentioned in Example 1, "All of the paths between these synchronous elements are then constrained with the timing specification TS_clk20, which specifies a 20 ns requirement from synchronous element to synchronous element and a HIGH 50% (clk20 has a 50/50 duty cycle)." My problem is how did you choose the value of "20 ns" requirement from synchronous element to sysnchronous element. How do we decide this requirement between FFS in any design?? please reply. This would help me in utilising the timing constraint in xilinx tool. Suraj Paul



How fast do you need your logic to go?  If it needs to execute 10 states of a state machine in 1 microsecond, then if each state is a clock cycle, that is 10 cycles in 1 us, or 10 MHz, or 100 nanoseconds.


What is it you want (need) to do?


Genrally, the slower the clock, the easier it is to meet timing, the less power you consume (device stays cooler), and the software tools run faster (as they are doing less work to place and route the design).


Slowest is best, fast enough to do the job, and no faster.




I was refering to this document to understand the usage of OFFSET IN and OFFESET OUT timng constraint. I have a query. The page 1 of this document says us: "Pad to Setup or OFFSET IN BEFORE constraint is used to ensure that the external clock and external input data meet the setup time on the internal flip-flop."

I wish to know how to get to know the Setup and hold time for internal FFs of the FPGA? Unless i know this fact i cant specify the OFFSET IN constraint in UCF. The subsequent examples mentioned in this document (page 7) assumes OFFSET requirement is 3 ns. How are these numerical figures decided? Please clarify this point.





Internal FF?  they are all internal.  Do you mean not an IO DFF?  The path to be taken is fully characterized, and the data is in the speeds file.  So, the tools know exactly what the timing is, from anywhere, to anywhere.  You do not need to know, as the tools, with the proper constraints, takes care of everything.

If you are still curious, you can examine any path's delay using FPGA_Editor.




Hi austin,

                  kindly correct my understanding if wrong.

We need to give the value of clock to Q delay of the external device interfacing with FPGA as offset IN constraint. 

Offset out is used to give the value of the path from the flipflop to pad by substracting the the setup value of the destinatioon device frm the clock.






Offset in tells the tools when the data arrives, from the outside, through to the inside of the FPGA device is valid.


Offset out tells the tools when the data should be valid that leaves the device (going from inside, to outside).



Xilinx Employee
Xilinx Employee



Great piece of info regarding constraints...  

For Timing constraints info, this could be a great platform to start for begineers..







      I am using the ipcore of QDRll+ of vexter 6 of xilinx. I want to check the controller with giving the constarits. i have given the period constarit it is ok. What more constarits can i use.

 i am in confuse which constarit to give and not give. I need a help from you




   I am using the ipcore of QDRll+ of vexter 6 of xilinx. I want to check the controller with giving the constraints. i have given the period constraints it is ok. What more constraints can i use.

 i am in confuse which constraintsto give and not give.



I need a help from you