Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users. In order to help those who have never had to constrain their timing, I continue with part 3 (of 5 parts) on timing constraints.
Tprop or Offset
The time it takes to get a signal from point A to point B is called the propagation time. It is based on the speed of light through a medium. For example, a trace on a printed circuit board carries signals at around 6 to 7 picoseconds per millimeter. Finding this time can be done by running simulations or solving equations when you know the dielectric constant for the material and the geometry of the wiring traces. Inside the silicon device the signals behave in much the same way, but also may be delayed by going through active circuits (buffers, inverters, logic and interconnect).
Often, you can also measure these times with the help of an oscilloscope. Propagation times generally do not vary much at all when the path has no active elements. If the path is in silicon, the strength of the transistors will cause the path delay to vary with both a maximum value and a minimum value. Timing needs to be met for both, obviously.
In order to tell the tools when data arrives at a particular location, offset constraints are used.
The OFFSET IN constraint defines the relationship of a clock and data as they enter the device:
OFFSET = IN 2 ns VALID 16 ns BEFORE “clk20";
This constraint tells the tools that data will be setup at PADs 2 ns before the clk20 rising edge, and that the data will remain valid for 16 ns after it arrives. This constraint only applies to PADs that go to registers that are clocked by clk20, or a derivative of clk20 (a derived constraint).
OFFSET requires a PERIOD constraint on clk20, so that it understands the clocking structure. This following is also acceptable:
OFFSET = IN 2 ns BEFORE “clk20";
However, the above statement will not check the hold time because we do not know when the data goes away at the PIN of the FPGA. If the data will not be setup until 2 ns after the clock edge, then we use the following:
OFFSET = IN -2 ns VALID 16 ns BEFORE “clk20"; # Do not use OFFSET IN AFTER
(the text after the # is a comment)
The OFFSET OUT constraint defines the amount time you need to ensure that data makes it out of the device after a clock transition at the input to the FPGA:
OFFSET = OUT 3 ns AFTER “clk20";
This constraint tells the tools that you need to ensure that data is at the output pin of the FPGA 3 ns after a clock transition at the input of the specified clock to the FPGA. This constraint only applies to PADs that are driven by registers that are clocked by clk20, or a derivative of clk20 (a derived constraint). OFFSET requires a PERIOD constraint on clk20, so that it understands the clocking structure. Hold times are not checked for OFFSET OUT.
If we need the data 2 ns before the clock edge, then we use the following:
OFFSET = OUT -2 ns AFTER “clk20"; # Do not use OFFSET OUT BEFORE
Next time: how to define and use groups and assign group names.