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Timing Constraints: Part 3 (of 5)

austin
Scholar
Scholar
8 7 15.6K

Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users.  In order to help those who have never had to constrain their timing, I continue with part 3 (of 5 parts) on timing constraints.

 

Tprop or Offset

The time it takes to get a signal from point A to point B is called the propagation time.  It is based on the speed of light through a medium.  For example, a trace on a printed circuit board carries signals at around 6 to 7 picoseconds per millimeter. Finding this time can be done by running simulations or solving equations when you know the dielectric constant for the material and the geometry of the wiring traces.  Inside the silicon device the signals behave in much the same way, but also may be delayed by going through active circuits (buffers, inverters, logic and interconnect).

Often, you can also measure these times with the help of an oscilloscope.  Propagation times generally do not vary much at all when the path has no active elements.  If the path is in silicon, the strength of the transistors will cause the path delay to vary with both a maximum value and a minimum value.  Timing needs to be met for both, obviously.

In order to tell the tools when data arrives at a particular location, offset constraints are used.

OFFSET_IN

The OFFSET IN constraint defines the relationship of a clock and data as they enter the device:

OFFSET = IN 2 ns VALID 16 ns BEFORE “clk20";

This constraint tells the tools that data will be setup at PADs 2 ns before the clk20 rising edge, and that the data will remain valid for 16 ns after it arrives.  This constraint only applies to PADs that go to registers that are clocked by clk20, or a derivative of clk20 (a derived constraint).

OFFSET requires a PERIOD constraint on clk20, so that it understands the clocking structure.  This following is also acceptable:

OFFSET = IN 2 ns BEFORE “clk20";

However, the above statement will not check the hold time because we do not know when the data goes away at the PIN of the FPGA.  If the data will not be setup until 2 ns after the clock edge, then we use the following:

OFFSET = IN -2 ns VALID 16 ns BEFORE “clk20"; # Do not use OFFSET IN AFTER

(the text after the # is a comment)

OFFSET_OUT

The OFFSET OUT constraint defines the amount time you need to ensure that data makes it out of the device after a clock transition at the input to the FPGA:

OFFSET = OUT 3 ns AFTER “clk20";

This constraint tells the tools that you need to ensure that data is at the output pin of the FPGA 3 ns after a clock transition at the input of the specified clock to the FPGA.  This constraint only applies to PADs that are driven by registers that are clocked by clk20, or a derivative of clk20 (a derived constraint).   OFFSET requires a PERIOD constraint on clk20, so that it understands the clocking structure.  Hold times are not checked for OFFSET OUT.

If we need the data 2 ns before the clock edge, then we use the following:

OFFSET = OUT -2 ns AFTER “clk20";
# Do not use OFFSET OUT BEFORE

Next time:  how to define and use groups and assign group names.

Austin Lesea



References:

Constraints Guide:  Constraint Syntax for UCF, PCF, and HDL
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf

Timing Constraints User Guide:  Conceptual information on how to constrain a design
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf

Timing Analyzer Help:  General information on how to use timing analyzer
http://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/timingan/timingan.htm

7 Comments
dp11
Adventurer
Adventurer

Hi Austin,

 

Can you have a look at the post in the Timing Analysis section and explain about how SKEW is calculated ?

 

Thanks

 

dp11 

drjohnsmith
Teacher
Teacher

Hi

 

your offset spec looks incomplete,

   in that it has no pin referance ?

 


OFFSET = IN 2 ns VALID 16 ns BEFORE “clk20";

 

could you do an example to clarify of say 

 

  8 input pins inp(7..0)

  one clock in ( clk )

 

what would the offset in specification be for the above 2ns / 16ns example ?

 

And if I had one output pin outp, with data must be out 10 ns after clock,

   how would the offsetout line look,

 

TA


waris.mohammad
Explorer
Explorer

hI AUSTIN,

                     you mention that offset canstraint can be applied to a derived clock too.

Consider this scenario:

i have 50Mhz clock input which is multiplied by 4 for running some logic.

The 200Mhz clock is then divided by 2(100Mhz) to run some other logic which is interfacing with external memory.

The same 100Mhz is also forwarded to the memory by ODDF(it is a synchronous SRAM).

I tried gving period consatrint for 100Mhz clock(clk100) and then used offset in constraint . I also gave offset out wiht out any value and reference pin is the forwarded clock pin.

But the toll complained that it does not find any net named clk100 and gave a note that offset can only be used with clocks which are externally entering to FPGA pin.

 

plz advice.

austin
Scholar
Scholar

w,

 

What version of the tools are you using?  Did you look through the manuals for that version?

 

 

waris.mohammad
Explorer
Explorer

ISE 10.1.

 

I have seen the manuals there is no clear mention about derived clocks.

smillertait
Visitor
Visitor
Hi Austin, Thanks for writing this series, it is a useful complement to UG612. One question for you: In the above post you have comments stating "do not use OFFSET IN AFTER" and "do not use OFFSET OUT BEFORE." Is this for a particular functional reason or is it simply to keep the constraints file more clear by using fewer variations of the OFFSET constraint? Thanks Shane
austin
Scholar
Scholar

s,

 

Yes.  To keep what you are doing clear, and concise, and not to confuse the tools!