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Timing Constraints: Part 4 (of 5)

Scholar austin
Scholar
4 1 9,656
Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users.  In order to help those who have never had to constrain their timing, I continue with part 4 (of 5 parts) on timing constraints.

Groups and Group Names


A time group is a way to identify a constraint for a collection of paths or nets between synchronous elements.  To add components to a time group, you would use:

TNM
TNM_NET

or
TIMEGRP

Paths are constrained by defining groups, and then giving requirements between those groups.  There are few constraints that do not require Time Groups, such as:

NET MAXDELAY

The Maximum Delay (MAXDELAY) attribute defines the maximum allowable delay on a net.

TNM – Timing Name

To add a component to a user defined group:

[NET|INST|PIN] object_name TNM = predefined_group identifier;

where
      object_name is the name of the element or signal to be grouped
      predefined_group is an optional keyword
      identifier can be any combination of letters, numbers, or underscores

Do not use reserved words such as FFS, LATCHES, and RAMS.  This variable is case sensitive (TNM=abc ? TNM=ABC).  TNM can be applied to any net, element pin, primitive, or macro.

Components can be part of more than one group:

my_ffs_group TNM can have the my_ff component in it

my_ffs_group2 TNM can also have the my_ff component in it

To create a group:

NET CLOCK TNM=clk_group;

Any Keyword element can be made into a group for timing purposes.  In this example, the net CLOCK is traced forward to the flip-flops (FFS).  These flip-flops are timing-named (TNM) with the name clk_group.  clk_group can now be referenced by this TNM in TIMESPECs.

One can create a group using an instance:

INST macro1 TNM = LATCHES latchgroup;

All LATCHES in the macro called macro1 will be in a group called latchgroup.

INST mymac TNM = RAMS memories;

All RAMS in the macro called mymac will be in a group called memories.

INST tester TNM = coverall;

All PADS, LATCHES, RAMS, and FFS in the macro called tester will be in a group called coverall.  For a complete listing of the predefined groups, search the applicable Constraints Guide for ‘predefined group.’

Suggestion

In general, the fewer constraints, the better.  Complex constraints can often cause more problems than they solve.  As well, some paths or nets may be non-critical, and you may wish to declare that no constraints should be applied to these nets.

TIG (timing ignore) constraints are used to remove things we don’t care about, or to remove constraints from a ‘false path.’

NET "rst" TIG;

This tells the tools that you do not need to constrain this path.  It is important so that the tools do not work to meet timing on paths that you do not care about.  Setting timing ignore on such paths will also reduce run times, and may improve the quality of the timing on the paths you do care about.

You can also use TIG with FROM:TO constraints:

TIMESPEC TS_my_fromto = FROM "my_to_grp" TO "FFS" TIG;


Next time, the last part, 5 of 5, will discuss timing on double data rate (DDR) interfaces.

Austin Lesea



References:

Constraints Guide:  Constraint Syntax for UCF, PCF, HDL
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf

Timing Constraints User Guide:  Conceptual information on how to constrain a design
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf

Timing Analyzer Help:  General information on how to use timing analyzer
http://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/timingan/timingan.htm
1 Comment
Adventurer
Adventurer

this is really helpfull for understanding thanks a lot for your great effort