PLD Blog (Archived) - Page 2

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

PLD Blog (Archived) - Page 2

austin
Scholar
Scholar

It has been a long time since I have posted anything on jitter, and a customer question to a Xilinx Field Applications Engineer (FAE) has prompted me to revisit an old friend, or foe.

Read more...

more
0 1 14.5K
austin
Scholar
Scholar

It has been a while since I last posted on my ‘favorite’ subject:  Soft Error Effects.  My excuse?  I have been busy.

Read more...

more
1 1 2,178
austin
Scholar
Scholar

I am going to take a moment and go back to some basics which perhaps have not been addressed in the training of some of the newer engineers who are now attempting to design their systems using Xilinx FPGA devices.

Read more...

more
4 13 32.9K
austin
Scholar
Scholar

“How to prototype an ASIC” is an old subject, but yet one that keeps coming up as the complexities and costs of ASIC’s increase.  If one wishes to reduce the risk when developing a new ASIC (application specific integrated circuit), then one has to prototype the circuitry in some fashion, and debug and test it. 

Read more...

more
0 3 4,816
austin
Scholar
Scholar

Availability is defined as the ratio of the time a system is working, divided by the time the system is working and not working.

Read more...

more
0 2 2,665
austin
Scholar
Scholar

In White Paper 286, I described the Rosetta program to design and test for soft errors.

Read more...

more
0 0 2,942
austin
Scholar
Scholar

Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users. In order to help those who have never had to constrain their timing, I conclude with part 5 on timing constraints. Read more...

more
2 6 10.8K
austin
Scholar
Scholar

Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users. In order to help those who have never had to constrain their timing, I continue with part 4 (of 5 parts) on timing constraints. Read more...

more
4 1 10.2K
austin
Scholar
Scholar

Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users. In order to help those who have never had to constrain their timing, I continue with part 3 (of 5 parts) on timing constraints. Read more...

more
8 7 15.6K
austin
Scholar
Scholar

Following along the forum traffic, it has come to my attention that timing constraints are often a mystery to new users. In order to help those who have never had to constrain their timing, I continue with part 2 (of 5) on timing constraints. Read more...

more
6 7 15.1K
austin
Scholar
Scholar

Following along the forum traffic, it has come to may attention that timing constraints are often a mystery to new users. Read more...

more
14 13 34.1K
austin
Scholar
Scholar

There are two sources of alpha particles and both cause upsets Read more...

more
0 0 6,013
austin
Scholar
Scholar

For this blog, I have invited John Latimer, a director of world-wide customer quality engineering, to provide us with a view of our philosophy in how we are improving our quality. Read more...

image1.gif
more
0 0 3,353
austin
Scholar
Scholar

What in the heck are we talking about? Read more...

more
0 0 3,350
austin
Scholar
Scholar

Recently I was asked to deliver a presentation on design techniques for a meeting with some customers. Just before I delivered my presentation, a friend from the Quality organization here at Xilinx presented on our quality. Read more...

more
0 0 2,980