07-04-2014 03:26 AM
I created a block diagram using Vivado Version 2013.3, which contains a Microblaze (version 9.2) and ancillary ip components.
I have compiled the complete design in Modelsim (version 12.d and 12.e) but I get the following error when loading modelsim.
# Loading work.system_lmb_bram_0(system_lmb_bram_0_arch)
# ** Fatal: (vsim-7) Failed to open VHDL file "system_lmb_bram_0.mem" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Process: /system_wrapper/system_i/microblaze_0_local_memory/lmb_bram/U0/native_mem_map_module/mem_map_module/line__3381
# FATAL ERROR while loading design
I created a file a .mem file "system_lmb_bram_0.mem" and placed it in the directory
but this did not solve the problem.
Does anyone have any idea where this issue is originating from and as to what possible course of action I could take to rectify it.
07-04-2014 04:25 AM
07-10-2014 04:24 AM