UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor meakerb
Visitor
3,036 Views
Registered: ‎12-12-2011

No warning if ROM_form file missing, and no output file generated.

I had a design that I copied into a new directory. I also put the KSPC6 files there, except that I missed putting the ROM_form.vhd file there. When I changed my PSM file and reassembled using kcpsm6.exe, my new code assembled with no errors or warnings. However, when I programmed my part, the old code was still there. It turns out that, without a ROM_form file, the assemble does not generate a <my_program>,vhd file (and in my case, the original one was still there).

 

Shouldn't there be a warning when no ROM_form file is found?

 

Tags (1)
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
3,028 Views
Registered: ‎09-05-2007

Re: No warning if ROM_form file missing, and no output file generated.

What you have observed and described accurately defines the behaviour of the KCPSM6 assembler. However, this was the intended and described behaviour  so I don’t think a warning message is necessary or appropriate (reference:  ‘Generation of VHDL and Verilog Files’ in the  ‘kcpsm6_assembler_readme.txt’ file).

 

That said, I do definitely understand the issue you faced and appreciate that it would have made you scratch your head for some time. However, I’m not convinced a warning would have been enough to make you notice either; our lives seem to have become so filled with warnings these days that we have a tendency to ignore them anyway. In your case you would like a VHDL file so you probably didn’t want it to generate a verilog file and therefore didn’t provide the ‘ROM_form.v’ template. Hence, if KCPSM6 did generate warning messages it would warn you every time that it didn’t write out a verilog file and you would get used to ignoring that and a new user might worry unnecessarily.

 

A suggestion for you to consider is invoking the KCPSM6 assembler from a batch file (see ‘kcpsm6_assembler_readme.txt’).  Your batch file could delete the old VHD file prior to running the assembler.

 

By the way if you used the KCPSM3 assembler in the past then you would know that you always had to provide 3 template files (‘ROM_form.vhd’, ‘ROM_form.v’ and ‘ROM_form.coe’) and it always  generated VHDL, Verilog and a coefficient file. It failed to complete if any template was missing so this would have saved you on this occasion. But please just let me say that KCPSM6 behaviour is different based on user feedback and experiences of KCPSM3 and so far it looks like it is an improvement. In fact, I can congratulate you on being the first person in nearly 2 years to report the potential for an issue within the context of file generation.

Ken Chapman
Principal Engineer, Xilinx UK
0 Kudos