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chapman
Xilinx Employee
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Registered: ‎09-05-2007

PicoBlaze FAQ – Multiple PicoBlaze Designs

PicoBlaze FAQ – Multiple PicoBlaze Designs

 

It is quite common to have more than one PicoBlaze in a design and several users have reported having 8 or more even in a small Spartan device. In the many cases these processor instances operate independently just as you might expect different sections of a hardware design to have their own controlling state machines.

There are no special challenges to including multiple PicoBlaze processors in a design. In essence, every processor is completely independent and it is only down to you if you want them to interact and any connectivity is totally your decision.

 

Obviously you need to ensure all instantiation instances of the KCPSM3, their associated program memories and all their connecting signals are unique. Either create different signal names such as ‘proc1_write_strobe’ and  ‘proc2_write_strobe’ or exploit hierarchy in your design which will hierarchically qualify all names to achieve the same unique names automatically. It makes sense to name each PicoBlaze program (PSM file) with a unique name as assembly results in the corresponding VHDL or Verilog description which you then include in your design project.

 

The following reference design for the Spartan-3E Starter Kit includes two PicoBlaze processors showing that this is all a straightforward design process.

 

http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

 

Low Cost Design Authentication for Spartan-3E FPGAs
This design introduces a low cost design authentication technique which can be an effective deterrent to prevent malicious copying of designs. The unique ID of the Intel StrataFlash parallel NOR memory is the key feature used in this design. Please note that this design is for the more experienced user of Spartan-3E FPGAs.

 

The only specific issue encountered when creating a design with more than one PicoBlaze is that JTAG_loader can only to update one program BRAM at a time during program development. This is where the DATA2MEM flow is often more suitable as this enables any program to be modified during a given iteration. In fact you could modify all instances at the same time but changing too much at the same time is not normally consistent with standard debugging procedures where you attempt to eliminate one issue at a time. A description of how to used DATA2MEM is supplied with PicoBlaze.

 

Of course it is just as likely that multiple PicoBlaze processors will require some degree of communication. Since everything is inside an FPGA, you are totally free to define the interconnection that your require and it is impossible to make any specific recommendations about what is the best ‘network format’ as it should all relate to the requirements of your application.

 

Probably the best advice I can provide is that you should try and adopt communication schemes that still enable each processor to work as independently as possible. In that way each processor becomes less time critical and that leads to an easier task when writing your programs. As such, the use of small FIFO buffers when passing data from one processor to another is ideal. PicoBlaze is provides with some UART macros and these contain 16-byte FIFO buffers. The FIFO buffers are defined by the VHDL and Verilog files named ‘bbfifo_16x9’ and this 16-byte FIFO macro can be used independently. The reference design indicated above shows ‘bbfifo_16x9’ being used to link two PicoBlaze processors and enable an ASCII message to be passed from one to the other.

 

Another popular communication scheme is to use a dual port BRAM. Each processor has full read/write access of the memory and therefore information can be shared or exchanged. Experienced users may consider replacing the 64-byte scratch pad with a connection to a BRAM to provide 256-bytes of scratch pad memory (2048-bytes when using something else to define the upper 3 address bits). The second port of the same BRAM is then connected to a second PicoBlaze which has also had its scratch pad memory removed. The advantage of this scheme is that all I/O ports remain available. Note this is not something for a novice and you really must work through any issues yourself if you attempt this technique.   

 

How about telling me how many processors you have in your design? I know a lot of MicroBlaze and PPC users also exploit PicoBlaze, but how many times?

 

Regards,

 

Ken Chapman

 

Ken Chapman
Principal Engineer, Xilinx UK
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aortega
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Registered: ‎10-24-2007

Hi Mr. Chapman! Thanks you for the design of KCPSM3. I think that is very clever!
I managed to fit 128 Picoblaze (With corresponding 1 Kb Instructions and 256 bytes of external memory) On a XUPV2P board that i happen to have. I am planning to do RC4 Cracking using them, In short I will be publishing the design and the source code (verilog and assembler) on my personal site.
I have some timings problems and the design won't run at the max speed of 200 MHZ, currently it only reaches 70 Mhz or so, but I am very new on FPGA design. In the future, i will post ask some questions in this forum with the hope that someone can help me to improve my design.

Regards,

Alfredo Ortega

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naylor
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Registered: ‎10-30-2007

I am working on a VLF radio design for through rock communications. The fast signal processing to perform single-sideband detection is done in logic (using System Generator). After filtering/demodulation/decimation, the data stream at audio rates can be handled by a processor such as the picoblaze for doing final agc/volume control etc. (plus cordic calculations to generate IQ voice components for emission). The device also has a user interface part that is nicely handled in another picoblaze processor. This generic structure I believe to be very powerful for many applications (DSP in logic/Picoblaze DSP treatment of filterred rate data/Picoblaze user interface). The user interface has a link to a serial port using Ken's UART and a small LCD using Ken's pico-code. The serial port is planned to be coupled via remote clients via bluetooth (headsets/mobile phones etc...) using the serial profile. In order to do program development and to allow future upgrades it is useful to download programs via the serial port (or across the bluetooth/serial link) as the jtag port will not be accesible. It is also necessary to re-program the two picoblazes. Here is a link to a bit of code that is preloaded on the user picoblaze that allows the user picoblaze to be re-loaded with a program starting at $20 (so only locations 0-$1F are lost for this bootloader) and to load the full program of the DSP picoblaze (which must be loaded first):
 
regards
Graham
 
nibbs
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quangngoc
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Registered: ‎01-09-2009

Hello

Now I have started study about soft CPU, as PicoBlaze and MicroBlaze. Can you help me which tools or software that I need to complete a project about embedded CPU. 

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bassman59
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quangngoc wrote:

Hello

Now I have started study about soft CPU, as PicoBlaze and MicroBlaze. Can you help me which tools or software that I need to complete a project about embedded CPU. 


To use MicroBlaze you must use the Xilinx EDK.

 

To use PicoBlaze, just download the assembler and the core.

 

There is a ton of available documentation about how to use both.

 

-a

----------------------------Yes, I do this for a living.
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quangngoc
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Only need ISE and EDK?

Do you think that I don't need buy a MicroBlaze core? I'm a starter. Can you tell me more specific?Thanks for your help

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quangngoc
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Hello!

Now I want build a embedded 8 bits CPU and other component as adder,FFT,... then connection them to build a system. Can I do it and how can I do it? Which tool or software I need? Thanks for your help.

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bassman59
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quangngoc wrote:

Only need ISE and EDK?

Do you think that I don't need buy a MicroBlaze core? I'm a starter. Can you tell me more specific?Thanks for your help


When you pay for the EDK, you get a royalty-free license to use the MicroBlaze in your designs. I believe that this is all made clear in the relevant documentation.

 

-a

----------------------------Yes, I do this for a living.
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quangngoc
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Thanks for your answer.
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digital_mind
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Registered: ‎09-03-2007

I have a design which introduces multi-picoblaze architicture on FPGA. You can find it at the following link: http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&thread.id=332

 

Regards

Mohamed Yousef

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Visitor
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Registered: ‎10-01-2007

I'm using Picoblaze for my research on lightweight interconnects for many-core architectures. On a Virtex-4 LX200 device, I placed a 16x16 mesh of Picoblazes, each one is attached to a simple programmable switch (the corresponding programming model is called "reconfigurable mesh"). The Picoblaze array is connected to a Microblaze core through Fast Simplex Links. The whole system runs at 100 MHz.
The programming model requires all Picoblazes to operate in lock-step, that is, the overall array synchronously executes phases of computation and communication. For better programmability I developed a compiler tool, that translates a single high-level specification (in short, a "subset" of C) into many psm-files that let the cores operate together.
As many of the (256) processing nodes might not be used during execution, I extended the Picoblaze by a stalling capability (by modifying the EN signals for the program counter and registers). With this, you can significantly reduce energy consumption.

Up to now, the project was focused on building a practical implementation of the reconfigurable mesh programming model on FPGA. The Picoblaze is a perfect vehicle for this because of its high programmability/footprint ratio. I published several papers on this work; if you are interested, just have a look at http://www.cs.uni-paderborn.de/fachgebiete/computer-engineering-group/people/giefers.html
Your comments and suggestions are always welcome!

Regards
 Heiner
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technicalman
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Registered: ‎01-23-2011

hi,

i work on pico Blaze now,and my program rom is full,so how i can expand the PB program rom? did i must use multiple kcpsm3 and each with its program rom? or there is another way? 

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chapman
Xilinx Employee
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Registered: ‎09-05-2007

Then the following FAQ would be better reading for you.....

 

 

PicoBlaze FAQ – Programs >1024 instructions

 

http://forums.xilinx.com/t5/PicoBlaze/PicoBlaze-FAQ-Programs-gt-1024-instructions/m-p/710

 

 

Since that FAQ was written we also have KCPSM6 for the Virtex-6 and Spartan-6 devices which supports programs up to 4K instructions. So use that if you are using newer devices.

 

 

 

 

Ken Chapman
Principal Engineer, Xilinx UK
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technicalman
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hi,

i work now on multiple picoblaze that i used 3 processors the first is master and the 2nd and 3rd is slave, the master should send commands to the two slaves, and i used two  fifo to link between each two processors. my problem is that the commands(data) send from master to slaves via fifo is not ok, there is some bytes arrived to slave and other not, so what i should do? should the maser or slave must reset the fifo after send or received  one byte ? i dont want to use interrupt for that  because i used it for generate PWM. please help....

thanks 

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eteam00
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Registered: ‎07-21-2009

should the master or slave must reset the fifo after send or received  one byte ?

A FIFO reset after sending a byte (but not receiving a byte) doesn't sound like a good idea.

A FIFO reset after receiving a byte (by the slave) sounds like a single-byte FIFO.

 

Have you run a simulation to debug your master-slave communications?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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technicalman
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Registered: ‎01-23-2011

 hi

 

i don't used simulation  but i check the received data on leds, i think the problem that there is no synchronization between the master and slave , in other design is operate the picoblaze with fifo of UART but with baud rate synchronization. how i get synchronization between them? i now try to reset the fifo after receiving one byte but i don't thik that will work

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eteam00
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Are you asking the forum to debug your design?  If it's a simple problem, you might get some useful help if you post your code.

 

On the other hand, it's difficult to provide a helpful answer to

'my three PicoBlaze cores don't work together, what's wrong?'

Suggest you use simulator to help you debug your design.  That's the use for which simulators are designed.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bassman59
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@technicalman wrote:

 hi @eteam00

 

i don't used simulation


Well, maybe you should consider using it.

 

----------------------------Yes, I do this for a living.
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technicalman
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Registered: ‎01-23-2011

the problem is not fixed, i try to use two fifos one for send and the other for receive but the problem still. if any one have an idia or structure example for linking the 3 or 2 processors? please Mr. Chapman i need your help

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eteam00
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the problem is not fixed, i try to use two fifos one for send and the other for receive but the problem still. if any one have an idia or structure example for linking the 3 or 2 processors? please Mr. Chapman i need your help

Nothing you have written in this thread suggests there is a problem with PicoBlaze 'core' design.  Absent such suggestion, the design problems are likely to be in your own design code.  Why would you ask Ken Chapman for help in debugging your design code?  At the very least, there isn't enough Ken Chapman to go around debugging every first-time FPGA design involving a PicoBlaze core.  Do you agree?

 

If you are interested in successfully pursuing the business of FPGA design (or any other design work, for that matter), you will need to learn how to debug your own designs.  You need to learn skills, techniques, and tools -- and how to apply them with cleverness.  You cannot separate out debugging from the rest of design work.  Debugging is part of design work, no two ways about it.

 

Isn't this a good time to learn how to debug (your) designs?

my three PicoBlaze cores don't work together, what's wrong?'

This is a question for you to answer.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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technicalman
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i now operate the processors successfully,i learned  the picoblaze and microblaze processors and most other fpga techniques,i used chipscope technique that i think it is best for debuging than simulation in ise, i was needed to complete my design in fast time so this was my problem and i fixed the design problem. thanks for your answer

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Registered: ‎10-24-2010

Hello everybody,

 

wanted to point to the mentioned issue.

Another thread is already on and gives a solution that works but as I already asked there (wrong place I was told) I'm wondering, if that really is THE solution, say editing something that rather is a black box to us.

 

So, what can the Picoblaze experts advise us?

 

Link to the thread:

http://forums.xilinx.com/t5/Synthesis/Keeping-Hierarchy-causes-packing-error-with-PicoBlaze-6/m-p/164588#M4364

 

Best regards,

Mark Radisson

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