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Xilinx Employee
Xilinx Employee
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Registered: ‎09-05-2007

Release 9 of KCPSM6 (What’s new?)

The ninth release of KCPSM6 is available for download from the PicoBlaze Lounge.

 

  1. xilinx.com/picoblaze

 

          Download ‘KCPSM6_Release9_30Sept14.zip

 

 

ISE, Vivado and UltraScale.

 

We are in a situation where Spartan-6 designs must be developed using the ISE tools but UltraScale and some Artix-7 designs must be developed using Vivado. Either tool can be used to develop the majority of 7-Series designs but there is a steady migration towards Vivado as that is the tool that will support new and future devices from Xilinx. For this reason, the most significant additions and adjustments to this KCPSM6 package relate to the use of PicoBlaze with both design tools.

 

The ‘READ_ME_FIRST.txt’ file will lead you in the right direction depending on the tool you must use or have elected to use. In simple terms, users of ISE will continue to use more or less the same package and documentation that has been used for the last 4 years. For Vivado users there is a new 30-page document (‘PicoBlaze_Design_in_Vivado.pdf’) that describes one way in which KCPSM6 can be successfully used in a Vivado project. In no way is this document intended to teach you how to use Vivado but it does present a detailed step by step method of implementing one of the reference designs that is included in the package and therefore it may be an example to help someone to become familiar with Vivado when getting started. Those experienced with Vivado are quickly lead to the most relevant pieces of KCPSM6 specific information so that they can include them to their own chosen design flow. The most important difference when using Vivado is to recognise that a new ‘ROM_form’ template (‘ROM_form_JTAGLoader_Vivado_2June14.vhd’) has been provided for use with the assembler. This template includes support for all (but only) the devices supported by Vivado including UltraScale.

 

 

Documentation

 

As well as the new documentation describing a Vivado design flow, a new 'Known_Issues_and_Workarounds.txt' file has been created. It appears that this often useful information was not noticed when it was part of the ‘READ_ME_FIRST.txt’ file so let’s see if it is noticed now!

 

 

Reference Designs

 

There are two additional reference designs included in this release.

 

'uart6_kc705' is a simple example of UART communication presented on the KC705 board. This design includes a scheme in which KCPSM6 can set the BAUD rate based on the clock frequency. A spreadsheet has also been provided to help those manually setting the BAUD rate of the UART macros.

 

‘kc705_kcpsm6_icap’ builds on the previous design and demonstrates communication and interaction with the Internal Configuration Access Port (ICAP) in a 7-Series device. This should be a useful reference for anyone interested in reading or writing configuration registers or the actual configuration memory. As presented, this design will have particular appeal to those interested in Single Event Upsets (SEU) and the SEM IP core.

 

 

The Hidden Star!

 

Thanks to a KCSPM6 expert and fanatic we now have an additional instruction to play with; 'STAR sX, kk'. This previously hidden instruction has now been added to the documentation and support has been included in the assembler and hardware simulation facilities.

 

For those wondering how this instruction ended up hidden and unknown even to me for nearly 4 years then here is the explanation. KCPSM6 has quite a few more instructions than KCPSM3 (e.g. ‘COMPARECY’, ‘OUTPUT kk, p’, ‘CALL@’ and ‘BANK’). Their addition increased the pressure on the encoding of bits in the op-codes for the whole instruction set, so initially I thought that the only way I would be able to implement a ‘STAR sX, sY’ instruction would be in the form of a modified ‘LOAD sX, sY’ instruction. ‘LOAD sX, kk’ uses 8-bits to define the ‘kk’ constant whereas the ‘LOAD sX, sY’ only requires 4-bits to define the ‘sY’ resister leaving 4-bits that are otherwise unused. I thought I would use one of those unused bits to differentiate a ‘LOAD sX, sY’ instruction from a ‘STAR sX, sY’ instruction without needing a completely separate op-code. From then on my instruction set tables only included an ‘STAR sX, sY’ instruction and 'STAR sX, kk' was forgotten. It turned out that I eventually managed to assign a unique op-code to ‘STAR’ so then both operand choices actually fell into place at the same time (i.e. the same logic is used for all similar pairs of instructions like ‘ADD sX, sY’ and ‘ADD sX, kk’).

 

So now that we have found the missing star, please enjoy ‘passing your tokens’ between register banks using it.

 

 

 

 

Keep having fun!

Ken Chapman
Principal Engineer, Xilinx UK
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