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Registered: ‎08-17-2013

obscure undocumented property of REGBANK instruction

I've found the hard way that REGBANK doe not immediately take effect when the next instruction is a read-modify-write on a register, such as:



AND s0, 07


in this example, s0 content is taken from the register bank that was in effect prior to the REGBANK A instruction (BANK B), and the result of the AND operation is stored in the BANK A.

2 Replies
Registered: ‎08-14-2007

That's cool! (not the undocumented part)  It means that you can move data from bank to bank with an instruction like:



AND s0, FF


-- Gabor
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Xilinx Employee
Xilinx Employee
Registered: ‎09-05-2007

Having checked it again, I still believe that REGBANK switches between banks of registers in the predictable way that was always intended. I set up the particular example that you presented and it worked in the way I would have expected it to work. I first loaded all registers in both banks with 32 different and recognisable values. Then I  executed REGBANK followed immediately by an AND instruction to modify the contents of the register in the newly selected bank and everything worked as expected.


If you run a simulation don't forget that there are a set of simulation only signals called 'sim_s0' etc to give you better visibility of register contents. See page 45 of 'KCPSM6_User_Guide_31March14.pdf' for details of simulation features.


As you know, every KCPSM6 instruction takes 2 clock cycles to execute. When a REGBANK instruction is presented to the 'instruction' input (e.g. op-code 37001 is REGBANK B), the decode takes place in the first clock cycle and defines the value of an internal signal called 'bank' on the next rising edge (i.e. half way through the 2-cycle process). On the second rising clock edge the value of 'bank' is used to select the register bank just as the next instruction arrives.


The 'STAR sX, sY' instruction is provided in order to pass information from one bank to another. As it happens, there has always been a hidden instruction; 'STAR sX, kk'. This will be documented and supported by the assembler in the next update (due for release on 30th September 2014) or available directly from me if you can't wait that long!



Ken Chapman
Principal Engineer, Xilinx UK
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