1 pulse per second physical output from IOPLL on ZCU102

[welcomelm]

 Hi I am looking for a 1 pulse per second  physical output driven from the internal IOPLL, which is being used as a ptp clock and is sampled by the TSU in GEM ethernet controller. The controller will generate an interrut for tsu_seconds_register_increment, which I can use to fire a software pps. But I am looking for hardware way to route that interrupt to a physical port (such as a GPIO on board) so that i can feed the pps to a oscilloscope.  I am Vivaldo dumy but I figure it can be done through FPGA design. Can someone share a insight? Thanks

[jg_bds]

You can configure the PSU to expose PTP and TSU signals to the PL.

-Joe G.

[welcomelm]

Thanks for answering. I did what you said and I found I can simply exposed the bits from emio_enet0_enet_tsu_timer_cnt that we need from probing (bit 45 and 46
for 1PPS) to an output header. I.E., tsu_timer_cnt[93:0] → Inverse of bit 45 is the 1PPS signal.

On the other hand, since I am new to this, I don't quite get what emio_enet0_enet_tsu_timer_cnt is. I know it is a 94 bit EMIO signal. But at this stage, is it already assigned to 94 GPIO pins? Where are these pins? And if I want to expose bit 45 to a existing pin on ZCU102, what do I do? Thanks

[jg_bds]

EMIO pins on the PSU only expose signals to the PL; they're not connected to external PL I/O unless you do that yourself, explicitly.

If you want only one bit of the 94-bit tsu_timer_cnt bus:

1. add a Slice IP to the block diagram containing the PSU
2. configure the Slice input to be 94 bits
3. configure the Slice output to be one bit (i.e., 45:45)
4. connect the input of the Slice to the PSU tsu_timer_cnt port/pin

You're now free to connect the Slice output to whatever you want, including a top-level I/O port to externalize it.

-Joe G.

[welcomelm]

Hi Thanks for your help

So I added the slice ip. How am I supposed to connect the slice's output to an top-level I/O port, say MIO23. Or PL I/O device pins.

Thanks

Min

[jg_bds]

PL signals cannot be sent to PS/PSU MIO pins.  They must leave the chip using PL I/O.

Select the Slice IP's output pin.  Press <Ctrl+T>. That will create an external I/O port. 

That port will pass through a top-level wrapper to become a system I/O.  After you run synthesis, open the synthesized design, in IO Planning format.

In the I/O Ports tab at the bottom of the Synthesized Design window, find the new port and assign it a technology/level and a pin location.

-Joe G.

[welcomelm]

Hi, I was finally able to assign PIN AG14 (which is a user LED on ZCU102) to the slice output,  the input is bit 45 of emio_enet0_enet_tsu_timer_cnt[0:93]. I was basing my design on the ps_emio_eth_1g from xapp1305 reference design with Vivaldo 2018.1 

On the other hand, after I loaded the bit file and the image to the board, the LED is not flashing in a 1pps rate. I did confirm that the ethnert is up and running find. I figured that I need to enable fmio_gem_tsu_clk_to_pl_bufg and fmio_gem_tsu_clk_from_pl for this to work, but after I got back to Vivaldo, I found the option of "tsu bufg and clock from pl" in PS-PL configuration is not available to choose. Do you have any idea why?

By the way, the pins are all configured LVCMOS18. Should I change them to LVCMOS33?

[jg_bds]

Yes; AG14 is in a 3.3-V powered bank, so you should change the IOSTANDARD to LVCMOS33.

How long is the 1PPS signal supposed to be active/asserted/high? The signal pulse needs to be long enough to turn the LED on, if you expect to see it that way.

Can you catch the signals on an ILA inside the FPGA?

-Joe G.

[welcomelm]

Yes the 1pps signal from IOPLL, which runs 250MHz, I guess it is too short the light up the LED.

I will have to hook up ILA tomorrow and let you know. Can you provide simple guidance about how to set up ILA for this test? Or if it is too complicated, can you recommend a tutorial?

Thanks

Min

[jg_bds]

Let me try, quickly:

• In your block diagram, select an internal net you want to instrument, and then right click. In the pop-up menu, select Debug. That net is now marked for debug. Repeat as needed.
• After you run synthesis, open the synthesized design. Below Open Synthesized Design in the Flow Navigator pane, select Set Up Debug.
• Struggle to get through that. Just kidding. It should be fairly easy. [Hint: For best results: 2k, 2, check, no check. Should make sense when you get there.]
• Save & then close the Synthesized Design, and then proceed with Implementation and bitstream creation.
• Open the Hardware Manager after you've programmed the device with the new bitstream. One of the things showing in the window will be the ILA you added.

Yeah... you'll have to seek out a tutorial for more details, I guess.

-Joe G.

[welcomelm]

Hi I have exposed emio_enet0_tsu_inc_ctrl[1:0] as a input, do you know how to force it to certain value from Vivaldo UI? Thanks.

[jg_bds]

I don't know much about a "Vivado UI", but I'd connect an input like that to an output.

Enable the PSU EMIO port. (If you set it up to be only 2 bits wide, you won't have to slice bits from it.) Connect the 2-bit 'o' outputs pins of the EMIO interface to the input pins you want to drive.  After configuring the EMIO pins, you only need to write a data register to twiddle the bits.

-Joe G.

[welcomelm]

The emio port that I want to drive is input

[jg_bds · Accepted solution]

Correction to my earlier post: Enable the PSU EMIO GPIO port. Take an output from that interface and connect it to your unconnected input.

-Joe G.

[welcomelm]

I was able to force the value by a constant ip. Now after the value is correctly set to the emio ctrl signal, I am able to get the pps signal and observe it through the DS38 LED on ZCU102. Thanks a lot for your help.

[raisinill]

Hi @welcomelm ,

I am struggling with a similar setup. Which value did you assign to the emio ctrl signal?