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akhiltthomas
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Registered: ‎01-31-2019

4 byte address restriction in Zynq7000 qspi

Hi,

I'm using zynq7000 with S25FL256L flash chip, all the 3 byte commands (QPP,QOR) works fine but extended addressing commands (4QPP,4QOR) which require 4 byte address fails.

Is there any restriction from the controller or limitation in handling 4 byte address? all the sample codes and examples for zynq7000 only seem to use 3 byte address.

Please let me know if any one has used this combination.

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u4223374
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Registered: ‎04-26-2015

Correct, the Zynq only does 3-byte addressing. That's why it's restricted to 16MB (see UG585).

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akhiltthomas
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Registered: ‎01-31-2019

I'm not using linear mode to read, I'm forming the spi commands manually and sending them. As per my understanding the 16MB restriction is for the memory-mapped access. Zynq should still be able to support a single flash of size > 16MB.

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ericv
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Registered: ‎04-13-2015

@akhiltthomas

although the controller only supports 3 byte addressing, all 4 byte addressing chips can be used 3 byte addressing because they have a "bank address" register.  Search in the datasheet for "bank addres register" and you'll get the commands related to that register..

 

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akhiltthomas
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@ericv

The flash chip i'm using does not have a bank register, it supports 4 byte address by either entering into 4 byte mode using 4BEN (0xB7) command or using extended addressing commands which specify the flash chip to expect 4 byte after instruction phahse

image.png

Previously i was using S25FL-S with the Bank register method, but the new chip S25FL-L doesn't support this.

all the example code in qspips are sending 3 byte address only.

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ericv
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Registered: ‎04-13-2015

@akhiltthomas

I did not know that one !

The controller does not have the capability to send 4 bytes addresses.  You could spoof the 4 addresses when writing by using the 1st data byte as the LSB address, making sure the # lanes for the data is the same as the # lanes of addresses, but for reading or erasing this doesn't work.  I did something alike that, which was skipping data bits, to overcome the "byte length" dummy cycles (i.e. only even # of dummy cycles with 4 lanes) when reading single chip (non-pair).

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ericv
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Registered: ‎04-13-2015

@akhiltthomas

It may be possible to get around the 3 byte address after all.  I'm no expert on the MIOs but if you enable the pull-up on the data lines, then through spoofing the address LSB will always be seen as 0xFF by the chip when reading.  You'll then have to skip the data you are not interested.  In the case of the erase, the lower address byte is in fact a don't care.  There may be more tweaking involved.

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