cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Participant
Participant
496 Views
Registered: ‎02-14-2019

4ns jitter on TSU timer output

Hi all,

I implemented PTP (ptp4l) on my ZYNQMP device (ZU4EV) according to  AR67239 (https://www.xilinx.com/support/answers/67239.html). I use  EMIO clock as GEM TSU clock (250MHz) generated by an MMCM from an internal 125MHz clock source (QPLL0). 

ptp4l is working and I can switch between slave and master mode with different configuration files.

My question is regarding ptp4l when my device is in PTP master mode.

I was expecting, that the TSU timer (emio_enet0_enet_tsu_timer_cnt) is incrementing with 4ns each TSU clock cycle since I'm connecting a 250MHz clock source (4ns period) to the timer. I connected emio_enet0_enet_tsu_timer_cnt[24] to an external I/O pin to monitor this 512ns (1.953125MHz) signal.

But, I observe each 73us a 516ns period instead of the nominal 512ns period. Why is this?

Regards,

Torsten

Tags (3)
0 Kudos
Reply
2 Replies
Participant
Participant
444 Views
Registered: ‎02-06-2018

Well i know nothing about ptp4l on ZYNQMP, however...

As a PTP slave, your observations would make sense if your 125MHz oscillator frequency was about 55ppm higher than nominal. Everything working as it should.

As a PTP 'Grandmaster', your 125Mhz oscillator would normally be locked to something like GPS, and your results would be strange. I would expect very very close to 1.953125Mhz on your i/o, with no 4ns jitter every 73uS, as you would be outputting 125M/64000. I doubt you intend to be a PTP Grandmaster with a free running 125MHz osc.

As a PTP master operating as a 'Boundary Clock' though, you would still be synced to incoming PTP, and your results would make sense, as for a PTP slave.

you could prove you are still locked to PTP in master mode : warm or cool your osc and see your 73us change

0 Kudos
Reply
Participant
Participant
402 Views
Registered: ‎02-14-2019

Thank you for your comments.

I first sync'ed as a PTP slave to a Grandmaster in my network (Linux-PC, running ptp4l as well). I then observed the same behavior (all 73us a 516ns period instead of nominal 512ns). My PTP slave reported a master offset of about 55000ns. This seems to be ok, my FPGA PTP slave oscillator is roughly 55ppm off.

I then stopped my PTP slave, changed the priority1 in my ptp4l.conf file and restarted PTP. I became a Grandmaster, all other participants in the network switched to my FPGA as new Grandmaster. But my TSU timer still generates the 512/516ns sequence.

It seems to be a ptp4l issue, what else do I have to become a Grandmaster without jitter? For now I don't care about my oscillator offset, it will be an isolated network, I just want to distribute the timing information to other network nodes.

0 Kudos
Reply