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Contributor
Contributor
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Registered: ‎03-11-2016

64bit AXI-DMA missing 4 bytes

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Hi,

 

I'm running into an issue with AXI DMA configured to 64bit S2MM but absent with default 32bit data width configuration.

 

The DMA was customized to only contain S2MM write channel in direct register mode, hence no SG function. The Address width is at default 32bit and Buffer length register at maximum 23 bit. The max burst size was set to 256 to increase bandwidth. The memory map data width and stream data width was propagated correctly from Zynq PS HP0 and AXI-S DATA FIFO correctly. Both at 64bit. 

 

After the correct number of bytes are transferred, I checked the memory data. It turned out that the latter 4 bytes in a 64 bits is always at zero. The first 4 bytes were correct. The DMA address was aligned to 32 bytes on ARM side.

 

I had ruled out any issues with my upstream custom IP by inserting ILA probe between AXI-S DATA FIFO and DMA. I also tried enabling the TKeep and force all 8 bits to 1 but it didn't make a difference. 

 

Thanks in advance!

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Contributor
Contributor
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Registered: ‎03-11-2016

It appears the problem resolves itself after I remake the hardware platform, base support package and application itself.

 

Maybe something during the ARM configuration determines the bus width of HP port.

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Teacher
Teacher
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Registered: ‎03-31-2012
have you checked the data between the dma & hp0 ? check if data is correct and verify the wstrb bits too.
If that is OK, verify HP0 is not set to 32 bits in PS configuration in the block diagram. If both checks out, show your system to a Xilinx FAE and let us know how they solve this mystery.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Contributor
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Registered: ‎03-11-2016

To follow on on the problem, I inserted ILA between DMA and AXI-mem-interconnect. Here are the results:

 

Attach 1 is the ILA probing between DMA and memory interconnect.

Attach 2 is the actual data from SDK after the transfer.

Attach 3 shows the HP0 port on Zynq is configured to be 64bit data with 32 addressing

 

The wstrb and data actually pass directly through the AXI memory interconnect to HP port based on the RTL schematics.

 

 Attach 4 is a new implementation with ILA between AXI-mem-interconnect and the HP port. The burst size break down to AXI3 doesn't seem to be wrong. 

 

ILA_DMA_out.png
Memory.png
RTL_PS.png
ILA-PS7010-HP0.png
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Contributor
Contributor
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Registered: ‎03-11-2016

It appears the problem resolves itself after I remake the hardware platform, base support package and application itself.

 

Maybe something during the ARM configuration determines the bus width of HP port.

View solution in original post

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