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aminfar1
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Registered: ‎01-09-2009

A coprocessor with multiple FSL ports

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I am trying to connect microblaze to a coprocessor. The coprocessor should get eight 32-bit input data in parallel and return a 32-bit result. Thus, I need eight Slave FSLs and a master FSL ports. Surprisingly, I realized that the coprocessor can only have one slave FSL and one master FSL. This is a ridiculous limitation. I do not want to write data to the coprocessor sequentially. How can I work around this limitation, and provide more Slave FSLs for the coprocessor? Can I manually define more Slave FSL for the processor with modifying HDL interface and MPD file.

 

XPS 11.3,  Virtex-5

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goran
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

Each BRAM block has two ports. One should be connected to your coprocessor, the other should be connected to the PLB through a xps_bram_if_cntlr.

Each xps_bram_if_cntlr will have a base address so all your 8 BRAM blocks will be memory mapped.

 

You can access these BRAMs by using normal pointers in C.

Just assign the pointers to the memory address you want to read or write.

 

Göran

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goran
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

You can just increase the number of FSL ports in the .mpd file and in the .vhdl entity.

 

But what will drive all the eight FSL slave ports?

You can connect all eight to MicroBlaze, but MicroBlaze can only put out a new value on one FSL port for each FSL instruction.

 

Göran

Message Edited by goran_bilski on 10-27-2009 11:09 AM
aminfar1
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Registered: ‎01-09-2009

Göran,

 

Yes, you are right. I've just realized that mircoblaze can only put out a value each cycle. I though that Microblaze is able to somehow provide SIMD capabilities, but I was wrong. So what is the other way to send multiple values in parallel to a coprocessor? Martin, in another post, has suggested that I use external RAM and design an interface to feed multiple values to the coprocessor. It makes my design complex and inefficient in terms of cost, even though I might eventually do that. Do you have any other suggestions to somehow provide multiple values for the coprocessor each cycle? In my application, SIMD operations and vector processing can dramatically improve performance.

 

Thanks,

aminfar

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goran
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

 

Providing eight new 32-bit values every clock cycle will require a very high throughput.

You will need very wide data busses like 128/256-bit wide.

 

MicroBlaze can't produce eight 32-bit words (which is 256-bit wide data), not sure even the latest Intel processor has that wide SIMD capabilities, some GPU might have it.

 

You can do internal wide memories using BRAM which could handle that kind of throughput but loading these BRAMs from external memory with new values will take longer time than it takes to consume the data from the BRAM. So you can only use them in bursts.

 

If you continously want eight 32-bit words every clock cycle, it will require extremely wide external memoriy interfaces (as graphic cards have). 

 

Göran

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aminfar1
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Registered: ‎01-09-2009

Göran,

 

I am trying to follow your method. So I added eight BRAM controllers and eight 32-bit wide BRAM blocks (The datawidth of BRAM should be the same as the PLB). So, one of the ports of BRAMs is accessed by the BRAM controllers and the other port is accessed by the coprocessor. It means there are eight parallel connections between BRAMs and the coprocessor. In this way, coprocessor can read eight parallel data each cycle. 

lets assume each BRAM holds an array of data. So we have eight arrays in eight BRAMS, array1, array2, array3 and so on. For the time being, lets don't worry about filling these BRAMS. For example, coprocessor can itself fill them up. 

However, these values should be accessible in the C program by the processor as well (through PLB or LMB controller or ...). Now, my question is that how I can specify in the linker or elsewhere that these eight arrays reside in the BRAMs (and not DLMB)? If it is not possible, then how I can access these arrays in my C program?

 

I really appreciate your help.

 

aminfar

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goran
Xilinx Employee
Xilinx Employee
6,653 Views
Registered: ‎08-06-2007

Hi,

 

Each BRAM block has two ports. One should be connected to your coprocessor, the other should be connected to the PLB through a xps_bram_if_cntlr.

Each xps_bram_if_cntlr will have a base address so all your 8 BRAM blocks will be memory mapped.

 

You can access these BRAMs by using normal pointers in C.

Just assign the pointers to the memory address you want to read or write.

 

Göran

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