08-20-2017 06:10 PM
I've read plenty of posts about this topic concerning the Zynq, but not much concerning the Zynq MPSoC yet. My question is can the Xilinx AXI DMA IP be configured to meet the transaction limitations for the ACP on the Zynq MPSoC, as specified in UG1085?
I have a simple design to transfer data between the DDR and the PL via an AXI DMA. When I connect it to the HP/HPC ports, all works perfectly. When I connect to the ACP, I get immediate BRESP SLVERR (before doing anything in baremetal SW) and then RRESP SLVERR upon starting a transfer.
I'm aware of the 16b/64b alignment, INCR transaction, and write strobe limitations of the ACP. I believe I'm complying with all of them (128b transfers from 0x00_7000_0000 to 0x00_7010_0000, multiple of page size transfers, and I only see 16-byte INCR transactions on the port).
I'm also aware of the restricted AxCACHE/AxUSER values, and I do have them manually set to 4'hf/4'h2 respectively, both legal values according to UG1085. To do this, I'm using the Constant IP on the expanded port in the block design, and I see the "connection to pin has been overridden by the user" messages on those pins. If I look in the schematic or run those same signals off the chip, I see 4'hf/4'h2. And yet, for reasons I don't understand, the ILA shows AxCACHE as 4'h3 (an unsupported value in UG1085).
So my next question: is this likely what is causing the SLVERRs, and if so, how would I go about fixing it? If not, anything else to check for?
08-29-2017 02:43 AM - edited 08-29-2017 02:43 AM
From the AXI specification from ARM:
SLVERR, slave error
The SLVERR response indicates an unsuccessful transaction.
To simplify system monitoring and debugging, this specification recommends that error responses are used only for error conditions and not for signaling normal, expected events. Examples of slave error conditions are:
Hope that helps,