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polaricsemi
Visitor
Visitor
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Registered: ‎03-11-2019

AHB to AXI bridge

AHB-AXI bridge put data on axi_wdata bus with different latency on diff cycles. In goes like 1-7-1-7-1-7-1-7... sequence, so each even data transfer misses and peripherals receive previous data as current, meanwhile, all other signals on AHB and AXI ports are stable(no difference between cycles). I've attached screenshots with examples.

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photo_2020-07-06_18-21-12.jpg
photo_2020-07-06_18-19-55.jpg
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abommera
Xilinx Employee
Xilinx Employee
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Registered: ‎10-12-2018

Hi @polaricsemi ,

>> Looking to ILA wavaform1, the m_axi_wready signal is asserted after the 6th clock cycle from data available on ahb bus (s_ahb_hwdata) which means that the slave is not ready to sample the data that is the reason you are observing latency on cycles. 

>> To be clear with this, Can you please provide the screenshot of back to back transactions (It would be great if 3 or 4 transactions for analysis instead of one) along with m_axi_wvalid signal?

Thanks & Regards
Anil B
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