cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
gi4you
Contributor
Contributor
773 Views
Registered: ‎09-24-2009

AR# 70413 DMA 64bit data width TX RX error

Jump to solution

Hello,

I am trying to zcu102 DMA 64-bit test based on AR# 70413.

https://www.xilinx.com/support/answers/70413.html

 

I tested memory map data width 32bit and stream data 32bit.

Next step, I changed memory map data width 64bit and stream data 64bit.

But I found error.

 

--- Entering main() ---
Initialize DMA engine
XAxiDma_HasSg
TxSetup
RxSetup
SetupIntrSystem
SendPacket
Wait TX done and RX done
Wait TDump registers A0000000:
Control REG: 640B7002
Status REG: 000B0049
Cur BD REG: 01010000
Tail BD REG: 010120C0

done and RX done
Failed test transmit not done, receive not done
--- Exiting main() ---

 

Thanks,

 

top.PNG
0 Kudos
1 Solution

Accepted Solutions
gi4you
Contributor
Contributor
664 Views
Registered: ‎09-24-2009

Hi @ demarco,

I tried to change the memory map data width 128 bit and stream data width 64bit.
This configuration is working for my test.

Thanks,

 

View solution in original post

dma_64b_128b_ok.PNG
0 Kudos
2 Replies
demarco
Xilinx Employee
Xilinx Employee
700 Views
Registered: ‎10-04-2016

Hi @gi4you ,

Based on this:

Status REG: 000B0049

You are getting a DMA Decode Error. That typically means you are attempting to access a memory location that doesn't exist in the memory map. You should double check the source and destination buffer addresses. If those seem okay, you might need to add ILAs to your design to determine exactly which memory access is causing a DECERR on the AXI interface.

To decode the status register bits, refer to PG021.

https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Regards,

Deanna

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
gi4you
Contributor
Contributor
665 Views
Registered: ‎09-24-2009

Hi @ demarco,

I tried to change the memory map data width 128 bit and stream data width 64bit.
This configuration is working for my test.

Thanks,

 

View solution in original post

dma_64b_128b_ok.PNG
0 Kudos