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Registered: ‎08-16-2014

ARM cache maintenance operations and the L2 cache

Is there an option to make the ARM cache maintenance operations (DCCMVAC etc.) affect the L2 cache as well?

The ARM architecture reference manual suggests that the ones operating to the point of coherence should, but they don't seem to do that in practice. I set bit 0 and 6 in the ACTLR. Are there any more bits that need to be set or is my only option to manually clean L2 caches using the MMIO interface?

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