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vgokhale
Explorer
Explorer
6,185 Views
Registered: ‎10-25-2011

AXI 4 Stream DMA loop back

I was doing some tests with the loopback example. I have a AXI 4 Stream type DMA. 

 

I have two problems - 

 

1) If I set the packet length to > 8192 my program never runs. It prints "Entering main" and gets stuck there. To solve this, I increased my heap and stack to 64 KB. I was wondering why this solves the problem though. My thought process was that these packets go over the heap and into the DDR. However, they shouldn't ALL sit on the heap before they start getting pulled out right? Shouldn't one or may be some get on the heap before they are sent to the memory? 

 

2) AFTER the above solution, I can run for larger packets. However, I cannot run multiple times. I can run only once. The first try passes and if I run again or set the #transfers to >1 it prints passed only once. I commented out

 

//while (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE)) {/* Wait */}

//while (XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) {/* Wait */}

 

to solve that. I get passed "transfer" number of times which means they all come back fine. So why does it get stuck on busy? If the DMA is busy, it wouldn't transfer or receive right? I know this has to do with the TLAST signal. However, I'm not able to figure out exactly what to do with that signal. I have currently set it to 1 depending on whether # of writes has been reached (0 if not).

 

Thank you.

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5 Replies
pepelats
Visitor
Visitor
6,155 Views
Registered: ‎05-29-2013

I have of the same problem (number 2). What is possible reason?

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vgokhale
Explorer
Explorer
6,139 Views
Registered: ‎10-25-2011

I have it narrowed down to the "idle" bit in the DMA's status register not being set. It is read-only, so I am trying to figure out what sets this bit. May be something in the hardware set ocrrectly makes the system set this bit but I have not figured out that part yet. If someone that has solved this problem or has knowledge of how the system sets the dma status register, I would appreciate it.
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henry.c
Adventurer
Adventurer
6,115 Views
Registered: ‎12-23-2012

I also have the similar problem (num. 2). DMA is always busy. The TLAST bit is set by hardware. Waiting for response

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jeffrey.johnson
Voyager
Voyager
4,991 Views
Registered: ‎02-07-2008

Try my walk-through for the AXI DMA connected to an AXI FIFO for loopback:

 

Using the AXI DMA in Vivado

 

I've shared the source code on Github here:

 

For ZedBoard here: https://github.com/fpgadeveloper/zedboard-axi-dma

For MicroZed here: https://github.com/fpgadeveloper/microzed-axi-dma

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kwsabas
Newbie
Newbie
421 Views
Registered: ‎02-27-2019

First thank you very much for your briefly example. Now i want to ask why to put a loopback FIFO with dma? 

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