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Registered: ‎01-15-2019

[AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

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Hi All,

I have two different Block Designs which should be connected in RTL. 

The first Block Design includes Zynq with GP AXI port. 

The second Block Design includes AXI Interconnect. 

The GP AXI port of the Zynq should be connected to the Slave Port of the AXI Interconnect (just name it AXI IC for short).

Here are mismatches between signals:

1) Zynq has the BID[11:0] and RID[11:0] input ports, which AXI IC doesn't 

2) AXI IC has the ARREGION[3:0] and AWREGION[3:0] output ports, which Zynq doesn't have

So, how to handle these ports? 

3) The ARREGION[3:0] and AWREGION[3:0] belong to the AXI4 standard... Could the AXI Interconnect be configured for AXI3?

4) Could the GP AXI port of  Zynq be configured for AXI3 as well as for AXI4? How? 

5) How to add one Block Design to another? 

Thank you!

 

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Registered: ‎11-09-2015

Re: [AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

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Hi @ldm.eth ,

The main thing to note is that the AXI interface of the Zynq-7000 is AXI3. This is hardened in the silicon and cannot be changed

 


@ldm.eth wrote:

Hi All,

I have two different Block Designs which should be connected in RTL. 

The first Block Design includes Zynq with GP AXI port. 

The second Block Design includes AXI Interconnect. 

The GP AXI port of the Zynq should be connected to the Slave Port of the AXI Interconnect (just name it AXI IC for short).

Here are mismatches between signals:

1) Zynq has the BID[11:0] and RID[11:0] input ports, which AXI IC doesn't 

[Florent] - You should be able to change the ID configuration for the AXI interconnect from the external AXI interface. Double click on the AXI interface of the BD (which is then connected to the IC). Then change the ID width. Finally, hit validate BD to propagate the parameter to the IC

AXI.JPG

2) AXI IC has the ARREGION[3:0] and AWREGION[3:0] output ports, which Zynq doesn't have

So, how to handle these ports? 

[Florent] - You mention it after, this is AXI4 standard while the Zynq-7000 AXI interfaces are following the AXI3 standard. This interface is optional for AXI4 and the spec recommend to set the default

3) The ARREGION[3:0] and AWREGION[3:0] belong to the AXI4 standard... Could the AXI Interconnect be configured for AXI3?

[Florent] - Yes, by the same way you couls change the ID width, you could change the BD external interface to AXI3 and the propagate to IC. The IC support AXI3/AXI4 and AXI4-Lite. It can do the interface between different interface types

4) Could the GP AXI port of  Zynq be configured for AXI3 as well as for AXI4? How? 

[Florent] - No, this is hardened on the silicon, thus it cannot be changed

5) How to add one Block Design to another? 

[Florent] - I am not sure to understand the question. If you ask how to had a BD inside another BD, then this is not supported. You would need to package one BD as IP to include it in another BD.

Thank you!

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: [AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

Jump to solution

Hi @ldm.eth ,

The main thing to note is that the AXI interface of the Zynq-7000 is AXI3. This is hardened in the silicon and cannot be changed

 


@ldm.eth wrote:

Hi All,

I have two different Block Designs which should be connected in RTL. 

The first Block Design includes Zynq with GP AXI port. 

The second Block Design includes AXI Interconnect. 

The GP AXI port of the Zynq should be connected to the Slave Port of the AXI Interconnect (just name it AXI IC for short).

Here are mismatches between signals:

1) Zynq has the BID[11:0] and RID[11:0] input ports, which AXI IC doesn't 

[Florent] - You should be able to change the ID configuration for the AXI interconnect from the external AXI interface. Double click on the AXI interface of the BD (which is then connected to the IC). Then change the ID width. Finally, hit validate BD to propagate the parameter to the IC

AXI.JPG

2) AXI IC has the ARREGION[3:0] and AWREGION[3:0] output ports, which Zynq doesn't have

So, how to handle these ports? 

[Florent] - You mention it after, this is AXI4 standard while the Zynq-7000 AXI interfaces are following the AXI3 standard. This interface is optional for AXI4 and the spec recommend to set the default

3) The ARREGION[3:0] and AWREGION[3:0] belong to the AXI4 standard... Could the AXI Interconnect be configured for AXI3?

[Florent] - Yes, by the same way you couls change the ID width, you could change the BD external interface to AXI3 and the propagate to IC. The IC support AXI3/AXI4 and AXI4-Lite. It can do the interface between different interface types

4) Could the GP AXI port of  Zynq be configured for AXI3 as well as for AXI4? How? 

[Florent] - No, this is hardened on the silicon, thus it cannot be changed

5) How to add one Block Design to another? 

[Florent] - I am not sure to understand the question. If you ask how to had a BD inside another BD, then this is not supported. You would need to package one BD as IP to include it in another BD.

Thank you!

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Registered: ‎01-15-2019

Re: [AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

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1) Thank you Florent for your response

2) Double clicking on the AXI Interface port opens the "Customize Port" window... Is there another way to open the "Customize Port" menu (besides double clicking on the port)? The RightClick on the port doesn't show the "Customize Port" menu... Honestly I expected that RightClick sldshow all the customization options...

3) When both the Zynq and AXI Interconnect are instantiated in the same Block Design and connected one to another (Zynq's GP AXI Master Port is connected to the AXI Interconnect Slave Port), during Block Design Validation all the parameters are propagated and the Ports become compatible (both become AXI3, etc). But, in the case when the Zynq and AXI Interconnect are instantiated in the different Block Designs, how is it possible to propagate the parameters between the AXI GP AXI Master Port and the AXI Interconnect Slave Port? If the Block Designs with Zynq and AXI Interconnect are packed as Custom IPs and instantiated to the same Block Design, will the parameters be propagated between these Custom IPs during the Validation process? Is there a way to exchange parameters between the Custom IPs in the same Block Design?

4) Actually the reason why the Zynq and AXI Interconnect were seperated to two different Block Designs, was so that the AXI Interconnect should be a part of the simulation and Zynq should not be... So, creation the different HDL wrapeprs for different Block Designs allows instantiation them in the different RTL hierarchies (one hierarchy is for the simulation and another one is not). Is there another way to include the AXI Interconnect in simulations and Zynq do not include while both of them are instantiated in the same Block Design?

Thank you!

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Re: [AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

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Hi @ldm.eth 


@ldm.eth wrote:

1) Thank you Florent for your response

2) Double clicking on the AXI Interface port opens the "Customize Port" window... Is there another way to open the "Customize Port" menu (besides double clicking on the port)? The RightClick on the port doesn't show the "Customize Port" menu... Honestly I expected that RightClick sldshow all the customization options...

[Florent] - Why is double clicking an issue for you? The right click menu is already quite long to add more options.

The other option would be to change the settings in the properties window when the interface is selected:

AXI.JPG

3) When both the Zynq and AXI Interconnect are instantiated in the same Block Design and connected one to another (Zynq's GP AXI Master Port is connected to the AXI Interconnect Slave Port), during Block Design Validation all the parameters are propagated and the Ports become compatible (both become AXI3, etc). But, in the case when the Zynq and AXI Interconnect are instantiated in the different Block Designs, how is it possible to propagate the parameters between the AXI GP AXI Master Port and the AXI Interconnect Slave Port? If the Block Designs with Zynq and AXI Interconnect are packed as Custom IPs and instantiated to the same Block Design, will the parameters be propagated between these Custom IPs during the Validation process? Is there a way to exchange parameters between the Custom IPs in the same Block Design?

[Florent] - You can do the parameters propagation only inside a single BD. If you package the BD with the interconnect, you know you will interface the zynq which as an AXI3 interface so you could fix this. Also you could add another interconnect between the packaged IP and the zynq. This way you do not really care about the interface type you have packaged.

4) Actually the reason why the Zynq and AXI Interconnect were seperated to two different Block Designs, was so that the AXI Interconnect should be a part of the simulation and Zynq should not be... So, creation the different HDL wrapeprs for different Block Designs allows instantiation them in the different RTL hierarchies (one hierarchy is for the simulation and another one is not). Is there another way to include the AXI Interconnect in simulations and Zynq do not include while both of them are instantiated in the same Block Design?

[Florent] - Not really, or at least I am not aware of this. Maybe try to ask this question on the simulation board if you want to confirm. Some people create a separated BD for simulation and design. What is the reason why you do not want the zynq in the BD?

Thank you!


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: [AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

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Florent wrote: "you could add another interconnect between the packaged IP and the Zynq. This way you do not really care about the interface type you have packaged."

It's not understood... I have two Block Designs in my project - the first one with Zynq and the second one is with AXI Interconnect ... Let's say I've packaged both of them to Custom IPs (Custom IP for each Block Design). So, how do you propose to connect them? Do you propose to put another AXI Interconnect between the packaged Zynq and packaged AXI Interconnect? Not understood...   

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Re: [AXI] ARREGION, AWREGION, BID, RID ports -> how to handle?

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Hi @ldm.eth ,

Do you propose to put another AXI Interconnect between the packaged Zynq and packaged AXI Interconnect?

[Florent] - Yes this is what I suggest. This way you can fixed the AXI Standard to whatever you want in each packaged IP. The AXI interconnect between both IP will do the interface.

But my main recommendation would be to package the IPs properly (i.e. set the AXI interface to AXI3 as you know you will interface a Zynq).


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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