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joe306
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Registered: ‎12-07-2018

AXI Address Map

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Hello, newbie here and need some help with the number of AXI Masters I should be using. I am using the Zynq Ultrascale+ MPSOC FPGA.

Here is what I have wired:

Block.jpg

I have three HPMx_FPD AXI interfaces out of the PS block. I didn't how many I needed so I included all available. So far in my design I have a bunch of I2C IP's, SPI IP's and I have a Display Port, Aurora IP and DDR4 memory on the PL-side.

Here is my Address Map:

Addr.jpg

I'm sure there are some experts our there that may say I only need one AXI Master output of the PS block. Or maybe not.

I was looking on page 226 of UG1085:

AXI_addr.jpg

I think I am only using M_AXI_HPM0_FPD (HPM0) interface and VCU bank. But I don't understand the other banks M_AXI_HPM0_FPD (HPM0) and M_AXI_HPM1_FPD (HPM1), seems there are double entries in the table.

Would it be better to have all the Low Power Peripherals such as I2C and SPI on the M_AXI_HPM0_LPD bank?

And on my Live Input Display Port(Target Generator) block and the Aurora IP be on the M_AXI_HPM0_FPD bank?

I'm sure this is an better way to do things, more optimized for my design.

Last, what is the max number of AXI slaves can you have in a design? I have three Master AXI outputs of the PS Block. I could route each to its own AXI Smart Connect block and each AXI Smart Connect block can have a max of 16 master interfaces. So the PS could control up to 48 AXI slaves on the PL-side. Is this reasonable?

Thank you very much,

Joe

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avcon_lee
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Registered: ‎07-17-2014

@joe306 

1.
Each peripheral on the PL side needs an address space, on which the CPU in PS can access the peripheral.
There are three access channels from PS to PL. each access channel has a fixed (or optional) start address and end address, which determines the range of access space.
For example, HPM0_LPD, whose address range is 0x8000_0000 to 0x9fff_ Ffff, the accessible size is 512MB.
And HPM1_FPD, its starting address can be selected as 0x4_0000_0000, you can also select 0x10_0000_0000, the difference is that you can access different sizes of space.

2.
Therefore, we decide how many access channels to use according to the size of the address space needed to access peripherals.
For example, when your peripheral needs less than 512MB of address space, you only need HPM0_LPD.
When it is larger than 512MB, HPM0_FPD can be selected.
In short, it is to select which access channel or the number of access channels to use according to the access space size

3.
Axi smart connect can be cascaded, so PS can access more than 48 peripherals on the PL side

View solution in original post

2 Replies
avcon_lee
Explorer
Explorer
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Registered: ‎07-17-2014

@joe306 

1.
Each peripheral on the PL side needs an address space, on which the CPU in PS can access the peripheral.
There are three access channels from PS to PL. each access channel has a fixed (or optional) start address and end address, which determines the range of access space.
For example, HPM0_LPD, whose address range is 0x8000_0000 to 0x9fff_ Ffff, the accessible size is 512MB.
And HPM1_FPD, its starting address can be selected as 0x4_0000_0000, you can also select 0x10_0000_0000, the difference is that you can access different sizes of space.

2.
Therefore, we decide how many access channels to use according to the size of the address space needed to access peripherals.
For example, when your peripheral needs less than 512MB of address space, you only need HPM0_LPD.
When it is larger than 512MB, HPM0_FPD can be selected.
In short, it is to select which access channel or the number of access channels to use according to the access space size

3.
Axi smart connect can be cascaded, so PS can access more than 48 peripherals on the PL side

View solution in original post

joe306
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Registered: ‎12-07-2018
Thank you very much for responding my message. I would like to see how your #3 is implemented. I will look around for any examples.

Thank you very much, I'm learning something new everyday.
Joe
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