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Scholar
Scholar
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Registered: ‎12-07-2018

AXI BRAM Controller/Block Memory Generator

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Hello, it is necessary to include a AXI BRAM Controller/Block Memory Generator with the Zynq Ultrascale MPSOC IP in the Block Design?

Does the MPSOC IP use the Memory for booting or initializing?

Last, is it required to have DDR4 connected to the PS side? I thought the MPSOC IP used the DDR4 for booting and initialization.

 

Thank you,

Joe

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @joe306 

No it is not required. The ZynqMPSoC as an On-Chip Memory to load the FSBL to initialize the system. Then you will probably have a DDR memory connected to the PS for your application.

The default example which is in vivado has a AXI GPIO IP and a AXI BRAM just to show a basic design which could have AXI4-lite and AXI4-MM interfaces but it is not required to have anything in the PL to be able to work with the ZynqMP processor


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
127 Views
Registered: ‎11-09-2015

HI @joe306 

No it is not required. The ZynqMPSoC as an On-Chip Memory to load the FSBL to initialize the system. Then you will probably have a DDR memory connected to the PS for your application.

The default example which is in vivado has a AXI GPIO IP and a AXI BRAM just to show a basic design which could have AXI4-lite and AXI4-MM interfaces but it is not required to have anything in the PL to be able to work with the ZynqMP processor


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Scholar
Scholar
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Registered: ‎12-07-2018

Thank you very much