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p.hayk
Observer
Observer
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Registered: ‎11-21-2013

AXI Burst Size meaning

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I am reading AXI doc, please help better understand the AXI, by answering my questions regarding to Burst transaction.

 

a) 
I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
When there are Bust length signals -AWLEN, ARLEN, which specifies the number of data transactions, whey we need another signal for burst size? 
Isn't the bust length info enough to specify how many transaction we need master to do?

b) Burst Address

Can someone please explain how AXI decides the next address of transaction in Bust mode? In the spec there is some equation, but I cannot clearly understand it.

 

Please see below the simulation waveform of Vivado example design, I want to understand the Burst behavioral here:

 

AXI_burst_write.png

 

Here the awaddr is always 0,  but burst type is 1 which means we are dealing with increment burst.

The behavioral of awlen, awsize signals are not clear for me. Also awcache signal is not clear

 

Can someone please explain

1) How many data will be written

2) In which addresses

3)  What is awcache value showing?

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demarco
Xilinx Employee
Xilinx Employee
9,998 Views
Registered: ‎10-04-2016

Hi @p.hayk,

The correct document to look at for the definition of all of these signals is the ARM AMBA AXI and ACE Protocol Specification (IHI0022E). You will need to create an ARM account to access the document.

https://silver.arm.com/download/download.tm?pv=1377613

 

The AxSIZE field indicates the maximum number of bytes to transfer on each data beat. This is an encoded field where 2^AxSIZE indicates this value. AWSIZE is 2 in your waveform, so this means each data beat is 2^2 = 4 bytes.

 

Since AWBURST is set to 1, you are doing an incrementing burst. In a multi-beat transfer, the first data beat will write to address 0x0, the second beat will write to address 0x4, the third to address 0x8, etc.

 

Your waveform shows several write commands with AWLEN set to 0. This indicates a single beat transfer. This means you are writing to address 0x0 many times.

 

Your waveform eventually issues several write commands with AWLEN set to 0xF. This indicates a 16 beat transfer. The burst will start writing data to address 0x0. The final beat of the transaction will write 4 bytes to address 0x3C.

 

AxCACHE indicates the memory type encoding. A setting of 0x3 indicates Normal Non-cacheable Bufferable memory type. Please refer to the ARM specification for a complete list of encodings.

 

Regards,

 

Deanna

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demarco
Xilinx Employee
Xilinx Employee
9,999 Views
Registered: ‎10-04-2016

Hi @p.hayk,

The correct document to look at for the definition of all of these signals is the ARM AMBA AXI and ACE Protocol Specification (IHI0022E). You will need to create an ARM account to access the document.

https://silver.arm.com/download/download.tm?pv=1377613

 

The AxSIZE field indicates the maximum number of bytes to transfer on each data beat. This is an encoded field where 2^AxSIZE indicates this value. AWSIZE is 2 in your waveform, so this means each data beat is 2^2 = 4 bytes.

 

Since AWBURST is set to 1, you are doing an incrementing burst. In a multi-beat transfer, the first data beat will write to address 0x0, the second beat will write to address 0x4, the third to address 0x8, etc.

 

Your waveform shows several write commands with AWLEN set to 0. This indicates a single beat transfer. This means you are writing to address 0x0 many times.

 

Your waveform eventually issues several write commands with AWLEN set to 0xF. This indicates a 16 beat transfer. The burst will start writing data to address 0x0. The final beat of the transaction will write 4 bytes to address 0x3C.

 

AxCACHE indicates the memory type encoding. A setting of 0x3 indicates Normal Non-cacheable Bufferable memory type. Please refer to the ARM specification for a complete list of encodings.

 

Regards,

 

Deanna

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