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Newbie
Newbie
666 Views
Registered: ‎07-24-2018

AXI_CHIP2CHIP with AURORA 8b10b

Hi,

    I am using z7015 and want to implement a AXI_chip2chip_bridge with aurora_8b10b PHY, the settings are as below.

When validating the block design, the AXIS data width automatically turns into 64bit thus requiring 2 serdes lanes and show a warning like:

[IP_Flow 19-4684] Expected long value for param C_AURORA_WIDTH but, float/scientific notation value 2.0 is provided. The value is converted to long type(2)

Does it mean that it's not possible to use only 1 lane while using 8b10b? How to solve that?

 

Thanks a lot

aurora.PNG
chip2chip.PNG
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3 Replies
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Newbie
Newbie
659 Views
Registered: ‎07-24-2018

Re: AXI_CHIP2CHIP with AURORA 8b10b

Message is like below

aurora.PNG
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Adventurer
Adventurer
644 Views
Registered: ‎05-23-2018

Re: AXI_CHIP2CHIP with AURORA 8b10b

I have a working Design that does exactly that. Make sure that your AXI-Master doesn't have threads (no BID, WID, AWID, ARID etc). 

 

The easiest way I found (if maybe not the best or fastest) is to use an AXI-DataWidth-Converter in front of the AXI-Chip2Chip. 

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Contributor
Contributor
318 Views
Registered: ‎01-16-2019

Re: AXI_CHIP2CHIP with AURORA 8b10b

is that work ?
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