07-25-2018 01:12 AM
I am using z7015 and want to implement a AXI_chip2chip_bridge with aurora_8b10b PHY, the settings are as below.
When validating the block design, the AXIS data width automatically turns into 64bit thus requiring 2 serdes lanes and show a warning like:
[IP_Flow 19-4684] Expected long value for param C_AURORA_WIDTH but, float/scientific notation value 2.0 is provided. The value is converted to long type(2)
Does it mean that it's not possible to use only 1 lane while using 8b10b? How to solve that?
Thanks a lot
07-25-2018 02:18 AM
I have a working Design that does exactly that. Make sure that your AXI-Master doesn't have threads (no BID, WID, AWID, ARID etc).
The easiest way I found (if maybe not the best or fastest) is to use an AXI-DataWidth-Converter in front of the AXI-Chip2Chip.