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Adventurer
Adventurer
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Registered: ‎07-14-2015

AXI Crossing 4K boundary

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I have two designs. One with Zynq Ultrascale+ and another one with Artix 7.

In Artix 7, I have implemented an AXI Master for reading and connected to DDR controller via AXI Interconnect. AXI Master crosses 4KB boundary in a single burst which is in clear violation of AXI spec. But as I learn from other posts, Xilinx AXI IC and DDR controller don't create an issue out of it. So it works fine. 

In Zynq US+, Same AXI master is connected to PL_HPD0. When the 4KB boundary is crossed, the AXI read data is not correct. The read data corresponds to some other memory location in the DDR. Burst length is 42 and the data width is 128 bits. Note that the incorrect data is present only for 4 beats in the middle of Burst. After that, the read data is correct even in the same burst. 

I am trying to figure out why it is different in these technologies. I guess that the Zynq US+ DDR controller is implemented on AXI3 and interconnect is also AXI which is causing the issue (why?). Is it correct?

Is there an IP available (like AXI Data FIFO or SmartConnect) which splits the transactions? I tried AXI SmartConnect since it mentions "Burst transactions are automatically split, as needed, to remain AXI compliant". But doesn't make any difference. 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @rakend_r 

If you do transactions that cross the 4K boundary then you will have unknown results. It will depend on the slave but most of the time this is not documented.

I guess what you see for the Smartconnect is just applicable when converting between AXI protocol but is not applicable if you are not following the AXI spec. Whatever the spec (AXI4 or AXI3), 4K boundary crossing is a violation so you should correct the Master not to send this type of transaction


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

HI @rakend_r 

If you do transactions that cross the 4K boundary then you will have unknown results. It will depend on the slave but most of the time this is not documented.

I guess what you see for the Smartconnect is just applicable when converting between AXI protocol but is not applicable if you are not following the AXI spec. Whatever the spec (AXI4 or AXI3), 4K boundary crossing is a violation so you should correct the Master not to send this type of transaction


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Adventurer
Adventurer
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Registered: ‎07-14-2015

@florentw 

Do you know why it is handled in AXI4 interconnect and DDR controller in 7 series and not in ZUS+ ?

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Scholar
Scholar
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Registered: ‎08-01-2012

The Xilinx Interconnect purely converts the transaction from one interface to another, so it does no checking as it is not the end point. The DDR controller can also be accessed without using AXI, hence why I think that works just fine. IIRC, the example testbench for the MIG (or IC, I cant remember) does an 8k read and write without issue.

as @florentw says, crossing a 4k boundary is breaking the spec, so never garanteed to work, and if do use it - it could be gone in any future release.

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Adventurer
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Registered: ‎07-14-2015

@richardhead 

Thanks for your reply. I understood that it violates the spec. But that question was just out of curiosity. 

Guessing both (7 series & US+) DDR controller is from Xilinx itself, why doesn't it work with ZUS+?  Is this solely due to the fact ZUS+ DDR controller (PS) works with AXI3 , not AXI4 (correct me if I'm wrong) and the 4KB limitation is due to AXI3?

https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/8554/axi-4-burst-boundary/29126#29126

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Moderator
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Registered: ‎11-09-2015

HI @rakend_r 

The link you are referring is not saying this is an issue only with AXI3... On the contrary it is saying that you will probably see this issue more frequently with AXI4. So it is absolutely not related to AXI4/AXI3.

Also I believe the components inside the zynq US+ are following AXI4 (different from Zynq-7000 which is AXI3)

It is just depending on the different component on the path. Some will not care and some will prevent you from breaking the spec.

Also when you go through the PS DDR controller, you go through multiple interconnect. So you cannot say if it is the DDR controller itself or the interconnects on the way

ZU+.PNG

Again, when you go outside the spec, the behaviour is unknown mainly because not tested or documented. So it is not really possible to explain where the difference is coming. You should just avoid doing it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar
Scholar
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Registered: ‎08-01-2012

@rakend_r 

I am using an AXI IC and MIG on US and US+ that breaks the 4k rule (same architecture in both). But all our masters are custom HDL ones. No problems here when violating the spec (for now).

We dont us any Zync devices though, so no onboard PS.

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Adventurer
Adventurer
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Registered: ‎07-14-2015

@richardhead 

That's good to know. 

 

Looks like PS DDR controller is entirely different than the usual ones. Wonder why !! 

Or it may be the AXI FIFO (AIF). !

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Scholar
Scholar
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Registered: ‎08-01-2012

Just to clear up what we're doing. Transactions are never longer than 4k, but its likely that 4k boundary crossings happen on a regular basis.

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Adventurer
Adventurer
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Registered: ‎07-14-2015
In my working scenario (in 7 Series), the burst length is small, but 4K is crossed in the middle of a burst which is in clear violation of the spec. I understand it results in undefined effects. But was just curious about ZUS+.