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Registered: ‎04-04-2018

AXI DMA DRC Warning after Synthesis and Implementation


I received the warning below after synthesis and impelemtation of my FPGA design. It is about BRAM collision within AXI DMA. However, I couldn't see any available configurations within the AXI DMA IP configutaion on the internal BRAM FIFO. So is there any way to solve this problem? or is it all right to ignore it?

Synchronous clocking is detected for BRAM
(xxxxxxxxxxxx/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design.
See the FPGA Memory Resources User Guide for additional information.


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