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bfung_2
Adventurer
Adventurer
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Registered: ‎07-02-2020

AXI DMA IP supports Incrementing Burst Write?

I'm trying to configure the AXI DMA to write a burst of 16 beats, each of 4B. I'm streaming in these 16 beats to the S2MM interface, asserting TLAST at the last beat. I was expecting, then, that the MM write interface would increment the address 0x4 each written beat, but it appears the address stays the same for all the beats the MM write interface writes. I'm wondering what I could be doing wrong?

Screenshot from 2021-04-19 22-46-12.png

You can see the 16 streaming beats into the S_AXIS_S2MM interface, and then the DMA master writing out the 16 beats on the M_AXI_S2MM interface. I can see the M_AXI_S2MM interface is configured with (AWBURST=1, AWLEN=15, AWSIZE=2 which is what I expect).

Just for completion, here is the test block design I'm using (AXI VIP mastering a DMA IP which writes data into a BRAM):

Screenshot from 2021-04-19 22-48-32.png

I've written 512 into the S2MM_LENGTH register.

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