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joseph.hancock
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Registered: ‎09-20-2013

AXI DMA MM2S transfer never initiated in Linux

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I'm utilizing AXI DMA similar to the design shared here. Following the dma_ex_polled standalone project shared earlier in the same forum I've been able to transfer data using the ZC706. I then ported that code for a simple Linux application which also works.

 

I'm now trying to get things working on a custom board. Here's what's strange. I'm able to transfer data using a standalone project but when issuing the MM2S transfer from Linux (using the same application as used on the ZC706) I get no response.

 

1) The first snapshot is of the ZC706 w/ Linux.

 

2) The snapshot below is on the custom board in standalone mode. For some odd reason the DMA engine appears to split the transfer into lengths of 0x37 and 0x47 (0x37+1 + 0x47+1 = 0x7F+1) even though the software issues the length once.

 

3) Lastly, the custom board (same bitstream) running Linux. The MM2S rvalid and tvalid never go high. There is no change to the lines other than what is illustrated.

 

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joseph.hancock
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Registered: ‎09-20-2013

I probed that end this morning and sure enough nothing was getting through to the PS.

 

I got it working today. The solution is one or a mixture of the following:

  1. made the HP clock and AXI DMA clock the same
  2. sent S2MM & MM2S to their own unique HP ports
  3. made DMA memory map 64 bits wide (from 32)
  4. my BIF may have been pointing to an old FSBL (ugh!)

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joseph.hancock
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Registered: ‎09-20-2013

I'm thinking the culprit is the FSBL, or ps7_init specifically. But how would I know what to change?

 

The ZC706 has a PS reference clock of 33.3 MHz; ours is at 50 MHz.

 

Both designs drive the AXI DMA ports (m_axi_mm2s_aclk and m_axi_s2mm_aclk) and corresponding interconnect ports with a 200 MHz clock.

 

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bwiec
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Registered: ‎08-02-2011
Hello,

It looks like those screenshots are probing the DMA. Is it possible to probe the other side of the interconnect (i.e. HP ports) to make sure the transaction is actually making it to the PS?

Are you using PS-generated resets for any/all of the PL logic in question?
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joseph.hancock
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Registered: ‎09-20-2013

I probed that end this morning and sure enough nothing was getting through to the PS.

 

I got it working today. The solution is one or a mixture of the following:

  1. made the HP clock and AXI DMA clock the same
  2. sent S2MM & MM2S to their own unique HP ports
  3. made DMA memory map 64 bits wide (from 32)
  4. my BIF may have been pointing to an old FSBL (ugh!)

View solution in original post

joseph.hancock
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Registered: ‎09-20-2013

Ok, it wasn't the FSBL. It still works using the old FSBL.

 

I had done #1 above but to no avail. It wasn't until after #2 & #3 (with #1 change included) that it worked.

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