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horacioneto
Participant
Participant
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Registered: ‎01-19-2016

AXI DMA - Multiple simultaneous accesses to the DDR

Hi there,

 

I want to implement a video system in Zynq where several image processing algorithms are applied (Gaussian Filter, Connected Components, Grassfire, etc). I want to use the PL portion of the Zynq, in order to directly connect the camera pins directly to the FPGA pins. After applying the image processing to the images caught by the camera module, I will store this in a memory location of the DDR. Then, a VGA controller will read the data from such memory location and display via a VGA port, present on Zybo board.

 

I am able to do all this, the camera captures image and in stream, all the image processing is applied and the overall result is stored on the DDR, and displayed via VGA port. However, I now want to store the original image along with the overall result and all of the intermediate steps. In this way, I would be able to dynamically choose which image should be displayed via VGA, whether the unprocessed image, the final result, or anything in between.

 

However, I do not know if this is possible. Hence, my questions are:

  1. Is it possible to do 2 or more writes to the DDR simultaneously (same cycle)?
  2. Is it possible to do 2 or more reads from the DDR simultaneously (same cycle)?
  3. Is it possible to do any combination of the two above? What is the limit?
  4. Is there any workaround to achieve what I want?

 

Thanks in advance ;)

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3 Replies
bwiec
Xilinx Employee
Xilinx Employee
3,104 Views
Registered: ‎08-02-2011

Hello,

 

It sounds to me like what you want to do is maintain multiple framebuffers in memory for intermediate calculations and then you'd only need to tell the VGA controller (which presumably is doing DMA) which framebuffer address to use. Is this what you're thinking?

 

So it sounds like the current architecture (PL hardware) is something like:

DMA Read -> Gaussian filter -> Grassfire -> ... -> DMA write

 

And you want to write the data, say, between gaussian filter and grassfire back to memory with additional DMA. Is this the context of your questions?

 

If so, then yes this is generally possible to do 'simultaneous' accesses like this. Combination of AXI interconnect in fabric and/or in the PS side will allow for arbitration of different ports to external DDR. As long as you have enough memory bandwidth (and interconnect bandwidth throughout the system) relative to the amount of data you need to write in a given frame period, then your system throughput can be maintained.

 

In practice, there are example designs out there showing several 1080p60 streams to/from DDR via HP ports in the PL (i.e. xapp741 shows 8 read/write streams https://www.xilinx.com/support/documentation/application_notes/xapp741-high-performance-video-AXI-interconnect.pdf). At VGA resolutions, you should be able to send many simultaneous streams.

www.xilinx.com
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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

zybo has a x32 ddr3 running at 1066 mbps/pin so slightly over 4 GB/s ddr bandwidth. PL has 4 HP ports which can talk to DDRC but only 2 ports. So if you are running 200 MHz 8 byte HP ports, full throttle access from PL is 3.2 GB/s which is probably doable if you plan your access patterns a little bit.

To answer your questions:

1) Yes, you can access from HP0 + HP2 into DDR simultaneously in the same cycle.

2) See 1.

3) Absolute maximum theoretical limit is the throughput calculation above.

4) If you want to maximize throughput,  you need to optimize your access patterns so that ddr page/bank open/close overhead is minimal.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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horacioneto
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Registered: ‎01-19-2016

Thanks for the fast replies, [b]bwiec[/b] and [b]muzaffer[[/b].

 

You understood correctly my questions and what I want to achieve. If I understand correctly, I only have to consider the maximum bandwidth available and arbitration of the data will be done by the DDR controller.

 

I should also think about my memory access patterns if going near the maximum bandwidth.

 

Thank you both, I do now understand this issue much clearer and now it's time to get my hands dirty and do some experiments.

 

Thanks :)

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