cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rudy
Explorer
Explorer
592 Views
Registered: ‎04-29-2010

AXI DMA Python API

Jump to solution

I am trying to do an AXI DMA to memory. But instead of using SDK to do the DMA driver, I was wondering if there are some simple ways to just call the driver by some python API commands? 

I know there is Pynq available, but on this specific platform that I am using, I am very limited, and cannot use Pynq. I am curious if there any Python based API for AXI DMA?

Thanks,

--Rudy 

 

Tags (4)
0 Kudos
1 Solution

Accepted Solutions
katsuki
Xilinx Employee
Xilinx Employee
520 Views
Registered: ‎11-05-2019

Hi @rudy 

Unfortunately there isn't, so you'll need to port the Python library or API for your board.

https://github.com/Xilinx/PYNQ/tree/master/sdbuild

Thank you
Don't forget to Reply, Kudo, and Accept as Solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

View solution in original post

Tags (1)
3 Replies
katsuki
Xilinx Employee
Xilinx Employee
521 Views
Registered: ‎11-05-2019

Hi @rudy 

Unfortunately there isn't, so you'll need to port the Python library or API for your board.

https://github.com/Xilinx/PYNQ/tree/master/sdbuild

Thank you
Don't forget to Reply, Kudo, and Accept as Solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

View solution in original post

Tags (1)
Rmccarty
Adventurer
Adventurer
503 Views
Registered: ‎09-05-2020

To start the axi dma in basic (not scatter/gather) mode, one simply writes 4 registers in the ip using the axi lite interface. Vivado will assign a base address for the dma axi lite interface and the dma ip data sheet contains the register descriptions and offsets.

I am using this with custom hls ip with the dma connected to the ACP port thru an axi bus matrix. The ACP insures cache coherency and all you need to do is write the destination address and data size and source address and size to the dma to start the process. It's that simple. No api/sdks or whatever needed at all. 

katsuki
Xilinx Employee
Xilinx Employee
426 Views
Registered: ‎11-05-2019

@Rmccarty 

The included sample program may be useful.

When you create an HW in Vivado and load the HW information (.XSA file) into Vitis, a BSP is created.

You can refer to the Example Program from the Vitis BSP view.

They are located in the installation directory data/embeddedsw/XilinxProcessorIPLib/drivers.

Thank you
Don't forget to Reply, Kudo, and Accept as Solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs