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jeffery_lim
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Registered: ‎11-07-2019

AXI DMA S2MM_LENGTH Register

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Hello,

I am having a hard time understanding how the AXI DMA IP determines how many bytes to transfer when you write into the S2MM_LENGTH register.

My current setup is a counter that increments every time the AXIS TREADY signal is high is sent into an AXI STREAM DATA FIFO IP, which is connected to the AXI DMA. So far, everything has worked, but what I'm finding is that I don't understand what I need to put into S2MM_LENGTH.

S2MM_LENGTH is in bytes, so the minimum value it needs to be is the max burst size. The AXI DMA IP says the max burst size is 256 words, so the minimum value of S2MM_LENGTH is 1024 (256 * 4 -> 1024 bytes).

I've confirmed this by writing 1024 into S2MM_LENGTH and the AXI DMA core finishes without an error. Anything less, and the error bit in the status register trigger.

Here is where I'm confused. If I set S2MM_LENGTH to be 2048 bytes, this means I will be getting 512 words, but when I read memory, I only get the same 256 words. If I read S2MM_LENGTH, it says it's only written 256 words.

What's the point of S2MM_LENGTH being so long, if no matter what value I put in it, it only transfer 256 words?

Is it because I am not using scatter gather mode? Or is there something I'm missing fundamentally about the core?

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dgisselq
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Registered: ‎05-21-2015

@jeffery_lim,

One of the features of the S2MM core that tends to surprise users of it is that the transfer ends on the first word having TLAST set.  This is to allow a transfer to be specified of an unknown or to be determined length.

Dan

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jeffery_lim
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Registered: ‎11-07-2019

To clarify, the counter's TLast goes high every 256 words, because I assumed that the max burst size required it.

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jeffery_lim
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Registered: ‎11-07-2019

Something I haven't tested, or thought about, is I have Allow Unaligned Transfers unchecked, could this be the problem?

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dgisselq
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Registered: ‎05-21-2015

@jeffery_lim,

One of the features of the S2MM core that tends to surprise users of it is that the transfer ends on the first word having TLAST set.  This is to allow a transfer to be specified of an unknown or to be determined length.

Dan

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jeffery_lim
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Registered: ‎11-07-2019

If TLast doesn't occasionally go high, then the AXI DMA core will hang. I was under the assumption that TLast had to be 256 due to the AXI DMA Max Burst, but I guess that's in relation to the AXI bus and not the AXI stream.

Secondly, the S2MM _LENGTH indicates the length in bytes of the buffer to write receive data. It says that the value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. If your packets are always constant size, you don't have to change the S2MM_LENGTH you request. If they change, then you need to adjust the value as you request DMA or just make it big and read the S2MM_LENGTH to see how much was transferred.

I'm going to be testing this theory out.

 

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dgisselq
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Registered: ‎05-21-2015

@jeffery_lim,

Is your goal to send packets or bytes?  If you just want to send a fixed number of words, there are open source alternatives to Xilinx's packet based processor that might fit your use pattern better.

Dan

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jeffery_lim
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Registered: ‎11-07-2019

I'm sending adc data over from PL to PS. I was able to collect more data once I moved the tlast to trigger on different words.

My alternate would probably be using a block ram controller, but I figured I would try the axi dma to learn it.

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