07-07-2017 08:58 AM
we are trying to send some data from the PL logic to DDR memory in a XCZU9EG Zynq UltraScale on a ZCU102 board. We are using an AXI Direct Memory Access IP block configured in Direct Register mode. We have build the following block diagram.
And we canfigured the AXI DMA as follows
Our problem is that when configuring AXI-DMA register, as datasheet explains, to start a block data movement to the DDR the processor gets halted when configuring the interruptions. We don't know where can be the problem or whether it is a HW or SW issue.
We would kindly appreciate any help to resolve this issue.
Here you can find the code to acces the DMA register and to initiate a S2MM transfer:
#define BYTES_REQUESTED 0x00000400
#define XPAR_AXI_DMA_1_BASEADDR 0x80000000
#define XPAR_AXI_DMA_1_HIGHADDR 0x8000FFFF
#define XAXIDMA_RX_OFFSET 0x00000030 //RX channel registers base
#define XAXIDMA_CR_OFFSET 0x00000000 // Channel control
if( init_dma() && (samples != NULL) )
XAxiDma_Out32( XPAR_AXI_DMA_1_BASEADDR + XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET, 0x00000001 );
//Start the S2MM channel running by setting the run/stop bit to 1 (S2MM_DMACR.RS =1)
XAxiDma_Out32( XPAR_AXI_DMA_1_BASEADDR + XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET, 0x00017001 );
//Enable the S2MM interrupt on complete interrupt enable & Interrupt on Delay Timer Interrupt Enable & Interrupt on Error //Interrupt Enable & Interrupt Threshold=0x01
destination = (u32)((u64)samples->data.buffer & 0xFFFFFFFF);
Xil_DCacheInvalidateRange( destination, BYTES_REQUESTED );
XAxiDma_Out32( XPAR_AXI_DMA_1_BASEADDR + XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET, destination );
//Destination address: 0x00100000
XAxiDma_Out32( XPAR_AXI_DMA_1_BASEADDR + XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET, BYTES_REQUESTED );
//Write the length in bytes of the receive buffer in the S2MM_LENGTH register=1024
07-11-2017 01:54 AM
First of all, verify If there is issue in the AXI_DMA register access itself, it could be because of addressing/clocking/reset.
You can use xsdb to test the register access.
07-18-2017 10:26 AM
07-25-2017 01:29 AM
Kravi and Bwiec,
thank you very much for your comments. I'll try to answer to your questions:
We guess, as you Bwiec have pointed out, the problem is with the destination address (0x00100000), which coincides with the place where the code is loaded. We have increased this address (#define MEM_BASE_ADDR 0x01000000) but we have not seen any evidence of improvement, it still hangs on the same line.
The fact is that we have changed our FPGA code since we've been struggling with this issue for a while. We are now testing a more simple approach to this issue. We have focussed on a previous discussion (Getting started with custom AXI Stream peripherals (Vivado)-571249) to try to get some samples saved on the DDR memory from the PL.
I'll get you informed.
Thank you very much for your time.
07-31-2017 02:09 AM
we are still testing the link between the PL and the PS in a Zynq Ultrascale+ through an AXI stream channel (S2MM) and we have found some strange behaviour that we don't understand:
Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, NUM_BYTES_REQUESTED, XAXIDMA_DEVICE_TO_DMA)
We still don't know how to solve this issue or at least whose fault is it. Could you be so kind to show some light on this issue?
Thank you so much for your time.
07-31-2017 07:27 AM
it seems we have finally resolved this issue. We can see the counter output on the RAM memory. However, we have changed several things on the custom IP that drives the data to the DMA (i.e., Data_process_0 in our case). These changes affect the automated generated code (when creating a new AXI4 peripheral) that rules the master port of the S2MM channel. We list below these changes in case somebody faces these same issues:
We hope somebody finds these comments useful.